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https://github.com/LadybirdBrowser/ladybird.git
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LibJIT: Use ModRM helpers where applicable
This also widens the argument coverage of some helpers, to allow memory offsets, this also consolidates the displacement size choosing. This also stops us from some out argument ordering bugs, as we now just need to look up the correct calling convention and call the correct function.
This commit is contained in:
Hendiadyoin1
Andreas Kling
parent
b46c5545f1
commit
540963fbe3
Notes:
sideshowbarker
2024-07-16 21:34:08 +09:00
Author: https://github.com/Hendiadyoin1
Commit: 540963fbe3
Pull-request: https://github.com/SerenityOS/serenity/pull/21658
Reviewed-by: https://github.com/awesomekling
1 changed files with 52 additions and 76 deletions
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@ -77,6 +77,11 @@ struct Assembler {
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return operand;
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}
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bool is_register_or_memory() const
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{
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return type == Type::Reg || type == Type::Mem64BaseAndOffset;
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}
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bool fits_in_u8() const
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{
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VERIFY(type == Type::Imm);
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@ -204,20 +209,20 @@ struct Assembler {
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VERIFY(count.fits_in_u8());
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0xc1);
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emit8(0xe8 | encode_reg(dst.reg));
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emit_modrm_slash(5, dst);
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emit8(count.offset_or_immediate);
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}
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void mov(Operand dst, Operand src, Patchable patchable = Patchable::No)
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{
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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if (src.reg == dst.reg)
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if (dst.is_register_or_memory() && src.type == Operand::Type::Reg) {
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if (src.type == Operand::Type::Reg && src.reg == dst.reg)
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return;
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x89);
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emit8(0xc0 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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emit_modrm_mr(dst, src, patchable);
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return;
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}
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@ -227,7 +232,7 @@ struct Assembler {
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// xor dst, dst
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? (1 << 0 | 1 << 2) : 0));
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emit8(0x31);
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emit8(0xc0 | (encode_reg(dst.reg) << 3) | encode_reg(dst.reg));
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emit_modrm_mr(dst, dst, patchable);
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return;
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}
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if (src.fits_in_u32()) {
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@ -244,37 +249,12 @@ struct Assembler {
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return;
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}
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if (dst.type == Operand::Type::Mem64BaseAndOffset && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x89);
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if (dst.reg <= Reg::RDI && dst.offset_or_immediate == 0) {
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emit8(0x00 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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} else if (dst.offset_or_immediate <= 127) {
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emit8(0x40 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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emit8(dst.offset_or_immediate);
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} else {
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emit8(0x80 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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emit32(dst.offset_or_immediate);
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}
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return;
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}
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Mem64BaseAndOffset) {
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if (dst.type == Operand::Type::Reg && src.is_register_or_memory()) {
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emit8(0x48
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| ((to_underlying(dst.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(src.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x8b);
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if (src.reg <= Reg::RDI && src.offset_or_immediate == 0) {
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emit8(0x00 | (encode_reg(dst.reg) << 3) | encode_reg(src.reg));
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} else if (src.offset_or_immediate <= 127) {
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emit8(0x40 | (encode_reg(dst.reg) << 3) | encode_reg(src.reg));
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emit8(src.offset_or_immediate);
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} else {
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emit8(0x80 | (encode_reg(dst.reg) << 3) | encode_reg(src.reg));
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emit32(src.offset_or_immediate);
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}
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emit_modrm_rm(dst, src, patchable);
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return;
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}
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@ -362,14 +342,10 @@ struct Assembler {
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void jump(Operand op)
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{
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if (op.type == Operand::Type::Reg) {
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if (to_underlying(op.reg) >= 8)
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emit8(0x41);
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emit8(0xff);
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emit8(0xe0 | encode_reg(op.reg));
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} else {
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VERIFY_NOT_REACHED();
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}
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if (to_underlying(op.reg) >= 8)
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emit8(0x41);
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emit8(0xff);
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emit_modrm_slash(4, op);
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}
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void verify_not_reached()
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@ -381,23 +357,23 @@ struct Assembler {
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void cmp(Operand lhs, Operand rhs)
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{
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if (rhs.type == Operand::Type::Imm && rhs.offset_or_immediate == 0) {
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if (lhs.type == Operand::Type::Reg && rhs.type == Operand::Type::Imm && rhs.offset_or_immediate == 0) {
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test(lhs, lhs);
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} else if (lhs.type == Operand::Type::Reg && rhs.type == Operand::Type::Reg) {
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} else if (lhs.is_register_or_memory() && rhs.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(rhs.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(lhs.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x39);
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emit8(0xc0 | (encode_reg(rhs.reg) << 3) | encode_reg(lhs.reg));
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} else if (lhs.type == Operand::Type::Reg && rhs.type == Operand::Type::Imm && rhs.fits_in_i8()) {
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emit_modrm_mr(lhs, rhs);
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} else if (lhs.is_register_or_memory() && rhs.type == Operand::Type::Imm && rhs.fits_in_i8()) {
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emit8(0x48 | ((to_underlying(lhs.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x83);
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emit8(0xf8 | encode_reg(lhs.reg));
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emit_modrm_slash(7, lhs);
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emit8(rhs.offset_or_immediate);
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} else if (lhs.type == Operand::Type::Reg && rhs.type == Operand::Type::Imm && rhs.fits_in_i32()) {
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} else if (lhs.is_register_or_memory() && rhs.type == Operand::Type::Imm && rhs.fits_in_i32()) {
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emit8(0x48 | ((to_underlying(lhs.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xf8 | encode_reg(lhs.reg));
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emit_modrm_slash(7, lhs);
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emit32(rhs.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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@ -406,17 +382,17 @@ struct Assembler {
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void test(Operand lhs, Operand rhs)
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{
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if (lhs.type == Operand::Type::Reg && rhs.type == Operand::Type::Reg) {
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if (lhs.is_register_or_memory() && rhs.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(rhs.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(lhs.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x85);
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emit8(0xc0 | (encode_reg(rhs.reg) << 3) | encode_reg(lhs.reg));
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} else if (lhs.type == Operand::Type::Reg && rhs.type == Operand::Type::Imm) {
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emit_modrm_mr(lhs, rhs);
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} else if (lhs.type != Operand::Type::Imm && rhs.type == Operand::Type::Imm) {
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VERIFY(rhs.fits_in_i32());
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emit8(0x48 | ((to_underlying(lhs.reg) >= 8) ? 1 << 0 : 0));
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emit8(0xf7);
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emit8(0xc0 | encode_reg(lhs.reg));
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emit_modrm_slash(0, lhs);
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emit32(rhs.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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@ -438,27 +414,27 @@ struct Assembler {
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// movsxd (reg as 64-bit), (reg as 32-bit)
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emit8(0x48 | ((to_underlying(reg) >= 8) ? 1 << 0 : 0));
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emit8(0x63);
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emit8(0xc0 | (encode_reg(reg) << 3) | encode_reg(reg));
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emit_modrm_rm(Operand::Register(reg), Operand::Register(reg));
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}
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void bitwise_and(Operand dst, Operand src)
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{
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// and dst,src
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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if (dst.is_register_or_memory() && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x21);
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emit8(0xc0 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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emit_modrm_mr(dst, src);
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm && src.fits_in_i8()) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x83);
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emit8(0xe0 | encode_reg(dst.reg));
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emit_modrm_slash(4, dst);
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emit8(src.offset_or_immediate);
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm && src.fits_in_i32()) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xe0 | encode_reg(dst.reg));
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emit_modrm_slash(4, dst);
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emit32(src.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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@ -468,21 +444,21 @@ struct Assembler {
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void bitwise_or(Operand dst, Operand src)
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{
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// or dst,src
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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if (dst.is_register_or_memory() && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x09);
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emit8(0xc0 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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emit_modrm_mr(dst, src);
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm && src.fits_in_i8()) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x83);
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emit8(0xc8 | encode_reg(dst.reg));
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emit_modrm_slash(1, dst);
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emit8(src.offset_or_immediate);
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm && src.fits_in_i32()) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xc8 | encode_reg(dst.reg));
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emit_modrm_slash(1, dst);
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emit32(src.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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@ -565,21 +541,21 @@ struct Assembler {
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void add(Operand dst, Operand src)
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{
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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if (dst.is_register_or_memory() && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x01);
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emit8(0xc0 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm && src.fits_in_i8()) {
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emit_modrm_mr(dst, src);
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} else if (dst.is_register_or_memory() && src.type == Operand::Type::Imm && src.fits_in_i8()) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x83);
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emit8(0xc0 | encode_reg(dst.reg));
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emit_modrm_slash(0, dst);
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emit8(src.offset_or_immediate);
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm && src.fits_in_i32()) {
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} else if (dst.is_register_or_memory() && src.type == Operand::Type::Imm && src.fits_in_i32()) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xc0 | encode_reg(dst.reg));
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emit_modrm_slash(0, dst);
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emit32(src.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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@ -590,14 +566,14 @@ struct Assembler {
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{
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if (dst.type == Operand::Type::Reg && to_underlying(dst.reg) < 8 && src.type == Operand::Type::Reg && to_underlying(src.reg) < 8) {
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emit8(0x01);
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emit8(0xc0 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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emit_modrm_mr(dst, src);
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} else if (dst.type == Operand::Type::Reg && to_underlying(dst.reg) < 8 && src.type == Operand::Type::Imm && src.fits_in_i8()) {
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emit8(0x83);
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emit8(0xc0 | encode_reg(dst.reg));
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emit_modrm_slash(0, dst);
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emit8(src.offset_or_immediate);
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} else if (dst.type == Operand::Type::Reg && to_underlying(dst.reg) < 8 && src.type == Operand::Type::Imm && src.fits_in_i32()) {
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emit8(0x81);
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emit8(0xc0 | encode_reg(dst.reg));
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emit_modrm_slash(0, dst);
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emit32(src.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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@ -614,21 +590,21 @@ struct Assembler {
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void sub(Operand dst, Operand src)
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{
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if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Reg) {
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if (dst.is_register_or_memory() && src.type == Operand::Type::Reg) {
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emit8(0x48
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| ((to_underlying(src.reg) >= 8) ? 1 << 2 : 0)
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| ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x29);
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emit8(0xc0 | (encode_reg(src.reg) << 3) | encode_reg(dst.reg));
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm && src.fits_in_i8()) {
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emit_modrm_mr(dst, src);
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} else if (dst.is_register_or_memory() && src.type == Operand::Type::Imm && src.fits_in_i8()) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x83);
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emit8(0xe8 | encode_reg(dst.reg));
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emit_modrm_slash(5, dst);
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emit8(src.offset_or_immediate);
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} else if (dst.type == Operand::Type::Reg && src.type == Operand::Type::Imm && src.fits_in_i32()) {
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} else if (dst.is_register_or_memory() && src.type == Operand::Type::Imm && src.fits_in_i32()) {
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emit8(0x48 | ((to_underlying(dst.reg) >= 8) ? 1 << 0 : 0));
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emit8(0x81);
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emit8(0xe8 | encode_reg(dst.reg));
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emit_modrm_slash(5, dst);
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emit32(src.offset_or_immediate);
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} else {
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VERIFY_NOT_REACHED();
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@ -649,7 +625,7 @@ struct Assembler {
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// call RAX
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emit8(0xff);
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emit8(0xd0);
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emit_modrm_slash(2, Operand::Register(Reg::RAX));
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if (!stack_arguments.is_empty())
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add(Operand::Register(Reg::RSP), Operand::Imm(align_up_to(stack_arguments.size(), 2) * sizeof(void*)));
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