Kernel: Detect Aarch64 virtual address bit width with CPU ID registers

This commit is contained in:
konrad 2023-01-08 12:22:47 +01:00 committed by Jelle Raaijmakers
parent 401fc6afae
commit 5791072280
Notes: sideshowbarker 2024-07-19 16:58:19 +09:00
4 changed files with 21 additions and 2 deletions

View file

@ -1504,4 +1504,20 @@ u8 detect_physical_address_bit_width()
}
}
u8 detect_virtual_address_bit_width()
{
auto memory_model_feature_register_2 = Aarch64::ID_AA64MMFR2_EL1::read();
switch (memory_model_feature_register_2.VARange) {
case 0b0000:
return 48; // 256TB
case 0b0001:
return 52; // 4PB (only for 64KB translation granule)
case 0b0010:
return 56; // 64PB (applies for FEAT_D128)
default:
VERIFY_NOT_REACHED();
}
}
}

View file

@ -278,5 +278,6 @@ StringView cpu_feature_to_description(CPUFeature::Type const&);
NonnullOwnPtr<KString> build_cpu_feature_names(CPUFeature::Type const&);
u8 detect_physical_address_bit_width();
u8 detect_virtual_address_bit_width();
}

View file

@ -34,6 +34,7 @@ void Processor::install(u32 cpu)
m_cpu = cpu;
m_features = detect_cpu_features();
m_physical_address_bit_width = detect_physical_address_bit_width();
m_virtual_address_bit_width = detect_virtual_address_bit_width();
initialize_exceptions(cpu);
@ -44,6 +45,7 @@ void Processor::initialize()
{
dmesgln("CPU[{}]: Supports {}", m_cpu, build_cpu_feature_names(m_features));
dmesgln("CPU[{}]: Physical address bit width: {}", m_cpu, m_physical_address_bit_width);
dmesgln("CPU[{}]: Virtual address bit width: {}", m_cpu, m_virtual_address_bit_width);
}
[[noreturn]] void Processor::halt()

View file

@ -89,8 +89,7 @@ public:
ALWAYS_INLINE u8 virtual_address_bit_width() const
{
TODO_AARCH64();
return 0;
return m_virtual_address_bit_width;
}
ALWAYS_INLINE static bool is_initialized()
@ -286,6 +285,7 @@ private:
u32 m_cpu;
CPUFeature::Type m_features;
u8 m_physical_address_bit_width;
u8 m_virtual_address_bit_width;
Thread* m_current_thread;
Thread* m_idle_thread;