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Kernel: Properly initialize NVMe admin queue depth
We were reading the value instead of setting it (as required by the specification). This worked only when we booted with a bootloader which initialized NVMe before us.
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parent
8a86218e25
commit
7339409575
Notes:
sideshowbarker
2024-07-17 14:36:19 +09:00
Author: https://github.com/IdanHo
Commit: 7339409575
Pull-request: https://github.com/SerenityOS/serenity/pull/24072
Reviewed-by: https://github.com/spholz
3 changed files with 10 additions and 19 deletions
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@ -145,13 +145,11 @@ ErrorOr<void> NVMeController::start_controller()
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return {};
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}
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UNMAP_AFTER_INIT u32 NVMeController::get_admin_q_dept()
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UNMAP_AFTER_INIT void NVMeController::set_admin_q_depth()
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{
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u32 aqa = m_controller_regs->aqa;
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// Queue depth is 0 based
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u32 q_depth = min(ACQ_SIZE(aqa), ASQ_SIZE(aqa)) + 1;
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dbgln_if(NVME_DEBUG, "NVMe: Admin queue depth is {}", q_depth);
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return q_depth;
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u16 queue_depth = ADMIN_QUEUE_SIZE - 1;
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m_controller_regs->aqa = queue_depth | (queue_depth << AQA_ACQ_SHIFT);
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}
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UNMAP_AFTER_INIT ErrorOr<void> NVMeController::identify_and_init_namespaces()
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@ -317,13 +315,13 @@ void NVMeController::complete_current_request([[maybe_unused]] AsyncDeviceReques
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UNMAP_AFTER_INIT ErrorOr<void> NVMeController::create_admin_queue(QueueType queue_type)
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{
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auto qdepth = get_admin_q_dept();
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OwnPtr<Memory::Region> cq_dma_region;
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Vector<NonnullRefPtr<Memory::PhysicalPage>> cq_dma_pages;
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OwnPtr<Memory::Region> sq_dma_region;
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Vector<NonnullRefPtr<Memory::PhysicalPage>> sq_dma_pages;
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auto cq_size = round_up_to_power_of_two(CQ_SIZE(qdepth), 4096);
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auto sq_size = round_up_to_power_of_two(SQ_SIZE(qdepth), 4096);
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set_admin_q_depth();
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auto cq_size = round_up_to_power_of_two(CQ_SIZE(ADMIN_QUEUE_SIZE), 4096);
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auto sq_size = round_up_to_power_of_two(SQ_SIZE(ADMIN_QUEUE_SIZE), 4096);
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auto maybe_error = reset_controller();
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if (maybe_error.is_error()) {
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dmesgln_pci(*this, "Failed to reset the NVMe controller");
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@ -362,7 +360,7 @@ UNMAP_AFTER_INIT ErrorOr<void> NVMeController::create_admin_queue(QueueType queu
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return maybe_error;
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}
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set_admin_queue_ready_flag();
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m_admin_queue = TRY(NVMeQueue::try_create(*this, 0, irq, qdepth, move(cq_dma_region), move(sq_dma_region), move(doorbell), queue_type));
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m_admin_queue = TRY(NVMeQueue::try_create(*this, 0, irq, ADMIN_QUEUE_SIZE, move(cq_dma_region), move(sq_dma_region), move(doorbell), queue_type));
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dbgln_if(NVME_DEBUG, "NVMe: Admin queue created");
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return {};
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@ -38,7 +38,6 @@ protected:
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public:
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ErrorOr<void> reset_controller();
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ErrorOr<void> start_controller();
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u32 get_admin_q_dept();
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u16 submit_admin_command(NVMeSubmission& sub, bool sync = false)
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{
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@ -61,6 +60,7 @@ private:
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NVMeController(PCI::DeviceIdentifier const&, u32 hardware_relative_controller_id);
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void set_admin_q_depth();
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ErrorOr<void> identify_and_init_namespaces();
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ErrorOr<void> identify_and_init_controller();
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NSFeatures get_ns_features(IdentifyNamespace& identify_data_struct);
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@ -77,15 +77,7 @@ static constexpr u32 CSTS_SHST(u32 x)
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return (x & CSTS_SHST_MASK) >> CSTS_SHST_SHIFT;
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}
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static constexpr u16 CC_AQA_MASK = (0xfff);
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static constexpr u16 ACQ_SIZE(u32 x)
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{
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return (x >> 16) & CC_AQA_MASK;
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}
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static constexpr u16 ASQ_SIZE(u32 x)
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{
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return x & CC_AQA_MASK;
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}
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static constexpr u16 AQA_ACQ_SHIFT = 16;
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static constexpr u8 CQ_WIDTH = 4; // CQ is 16 bytes(2^4) in size.
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static constexpr u8 SQ_WIDTH = 6; // SQ size is 64 bytes(2^6) in size.
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static constexpr u16 CQ_SIZE(u16 q_depth)
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@ -106,6 +98,7 @@ static constexpr u16 CQ_STATUS_FIELD(u16 x)
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return (x & CQ_STATUS_FIELD_MASK) >> 1;
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}
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static constexpr u16 ADMIN_QUEUE_SIZE = 2;
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static constexpr u16 IO_QUEUE_SIZE = 64; // TODO:Need to be configurable
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// IDENTIFY
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