diff --git a/Kernel/Devices/Storage/NVMe/NVMeController.cpp b/Kernel/Devices/Storage/NVMe/NVMeController.cpp index bd2f095fe2e..cfa43554847 100644 --- a/Kernel/Devices/Storage/NVMe/NVMeController.cpp +++ b/Kernel/Devices/Storage/NVMe/NVMeController.cpp @@ -145,13 +145,11 @@ ErrorOr NVMeController::start_controller() return {}; } -UNMAP_AFTER_INIT u32 NVMeController::get_admin_q_dept() +UNMAP_AFTER_INIT void NVMeController::set_admin_q_depth() { - u32 aqa = m_controller_regs->aqa; // Queue depth is 0 based - u32 q_depth = min(ACQ_SIZE(aqa), ASQ_SIZE(aqa)) + 1; - dbgln_if(NVME_DEBUG, "NVMe: Admin queue depth is {}", q_depth); - return q_depth; + u16 queue_depth = ADMIN_QUEUE_SIZE - 1; + m_controller_regs->aqa = queue_depth | (queue_depth << AQA_ACQ_SHIFT); } UNMAP_AFTER_INIT ErrorOr NVMeController::identify_and_init_namespaces() @@ -317,13 +315,13 @@ void NVMeController::complete_current_request([[maybe_unused]] AsyncDeviceReques UNMAP_AFTER_INIT ErrorOr NVMeController::create_admin_queue(QueueType queue_type) { - auto qdepth = get_admin_q_dept(); OwnPtr cq_dma_region; Vector> cq_dma_pages; OwnPtr sq_dma_region; Vector> sq_dma_pages; - auto cq_size = round_up_to_power_of_two(CQ_SIZE(qdepth), 4096); - auto sq_size = round_up_to_power_of_two(SQ_SIZE(qdepth), 4096); + set_admin_q_depth(); + auto cq_size = round_up_to_power_of_two(CQ_SIZE(ADMIN_QUEUE_SIZE), 4096); + auto sq_size = round_up_to_power_of_two(SQ_SIZE(ADMIN_QUEUE_SIZE), 4096); auto maybe_error = reset_controller(); if (maybe_error.is_error()) { dmesgln_pci(*this, "Failed to reset the NVMe controller"); @@ -362,7 +360,7 @@ UNMAP_AFTER_INIT ErrorOr NVMeController::create_admin_queue(QueueType queu return maybe_error; } set_admin_queue_ready_flag(); - m_admin_queue = TRY(NVMeQueue::try_create(*this, 0, irq, qdepth, move(cq_dma_region), move(sq_dma_region), move(doorbell), queue_type)); + m_admin_queue = TRY(NVMeQueue::try_create(*this, 0, irq, ADMIN_QUEUE_SIZE, move(cq_dma_region), move(sq_dma_region), move(doorbell), queue_type)); dbgln_if(NVME_DEBUG, "NVMe: Admin queue created"); return {}; diff --git a/Kernel/Devices/Storage/NVMe/NVMeController.h b/Kernel/Devices/Storage/NVMe/NVMeController.h index bfee2b667c5..e5e6c44ff1a 100644 --- a/Kernel/Devices/Storage/NVMe/NVMeController.h +++ b/Kernel/Devices/Storage/NVMe/NVMeController.h @@ -38,7 +38,6 @@ protected: public: ErrorOr reset_controller(); ErrorOr start_controller(); - u32 get_admin_q_dept(); u16 submit_admin_command(NVMeSubmission& sub, bool sync = false) { @@ -61,6 +60,7 @@ private: NVMeController(PCI::DeviceIdentifier const&, u32 hardware_relative_controller_id); + void set_admin_q_depth(); ErrorOr identify_and_init_namespaces(); ErrorOr identify_and_init_controller(); NSFeatures get_ns_features(IdentifyNamespace& identify_data_struct); diff --git a/Kernel/Devices/Storage/NVMe/NVMeDefinitions.h b/Kernel/Devices/Storage/NVMe/NVMeDefinitions.h index b97387fcf4e..890ab84a3fa 100644 --- a/Kernel/Devices/Storage/NVMe/NVMeDefinitions.h +++ b/Kernel/Devices/Storage/NVMe/NVMeDefinitions.h @@ -77,15 +77,7 @@ static constexpr u32 CSTS_SHST(u32 x) return (x & CSTS_SHST_MASK) >> CSTS_SHST_SHIFT; } -static constexpr u16 CC_AQA_MASK = (0xfff); -static constexpr u16 ACQ_SIZE(u32 x) -{ - return (x >> 16) & CC_AQA_MASK; -} -static constexpr u16 ASQ_SIZE(u32 x) -{ - return x & CC_AQA_MASK; -} +static constexpr u16 AQA_ACQ_SHIFT = 16; static constexpr u8 CQ_WIDTH = 4; // CQ is 16 bytes(2^4) in size. static constexpr u8 SQ_WIDTH = 6; // SQ size is 64 bytes(2^6) in size. static constexpr u16 CQ_SIZE(u16 q_depth) @@ -106,6 +98,7 @@ static constexpr u16 CQ_STATUS_FIELD(u16 x) return (x & CQ_STATUS_FIELD_MASK) >> 1; } +static constexpr u16 ADMIN_QUEUE_SIZE = 2; static constexpr u16 IO_QUEUE_SIZE = 64; // TODO:Need to be configurable // IDENTIFY