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Kernel/IntelGraphics: Move pipe management to the Transcoder class

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It became apparent to me that future generations of the Intel graphics
chipset utilize the same register set as part of the Transcoder register
set. Therefore, it should be included now in the Transcoder class.
This commit is contained in:
Liav A 2022-04-01 12:52:49 +03:00 • committed by Andrew Kaster
parent 2def16a3d2
commit 8042ae43c3
Notes: sideshowbarker 2024-07-17 10:54:57 +09:00
7 changed files with 95 additions and 122 deletions
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29
Kernel/Graphics/Intel/Transcoder/DisplayTranscoder.h
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@ -48,6 +48,7 @@ public:
u32 n1_link;
u32 m2_link;
u32 n2_link;
u32 pipe_conf;
};
ErrorOr<void> set_mode_setting_timings(Badge<IntelDisplayConnectorGroup>, DisplayConnector::ModeSetting const&);
@ -55,6 +56,10 @@ public:
virtual ErrorOr<void> enable_dpll_without_vga(Badge<IntelDisplayConnectorGroup>) = 0;
virtual ErrorOr<void> disable_dpll(Badge<IntelDisplayConnectorGroup>) = 0;
ErrorOr<void> disable_pipe(Badge<IntelDisplayConnectorGroup>);
ErrorOr<void> enable_pipe(Badge<IntelDisplayConnectorGroup>);
bool pipe_enabled(Badge<IntelDisplayConnectorGroup>) const;
ShadowRegisters current_registers_state() const;
virtual ~IntelDisplayTranscoder() = default;
@ -83,9 +88,31 @@ protected:
u32 n2_link;
};
explicit IntelDisplayTranscoder(Memory::TypedMapping<TranscoderRegisters volatile>);
struct [[gnu::packed]] PipeRegisters {
u32 pipe_display_scan_line;
u32 pipe_display_scan_line_count_range_compare;
u32 pipe_configuration;
u32 reserved;
u32 pipe_gamma_correction_max_red;
u32 pipe_gamma_correction_max_green;
u32 pipe_gamma_correction_max_blue;
u32 reserved2[2];
u32 pipe_display_status;
u32 reserved3[2];
u32 display_arbitration_control;
u32 display_fifo_watermark_control1;
u32 display_fifo_watermark_control2;
u32 display_fifo_watermark_control3;
u32 pipe_frame_count_high;
// Note: The specification calls this "Pipe Frame Count Low and Pixel Count"
u32 pipe_frame_count_low;
};
IntelDisplayTranscoder(Memory::TypedMapping<TranscoderRegisters volatile>, Memory::TypedMapping<PipeRegisters volatile>);
mutable Spinlock<LockRank::None> m_access_lock;
ShadowRegisters m_shadow_registers {};
Memory::TypedMapping<TranscoderRegisters volatile> m_transcoder_registers;
Memory::TypedMapping<PipeRegisters volatile> m_pipe_registers;
};
}