From 8ab601f9e148db2d8f331054a330de1f157b9304 Mon Sep 17 00:00:00 2001 From: Andreas Kling Date: Tue, 7 Jul 2020 21:35:23 +0200 Subject: [PATCH] UserspaceEmulator: Implement XOR_RM32_reg32 Note that this is a partial implementation since we don't have support for memory r/m variants yet. --- DevTools/UserspaceEmulator/SoftCPU.cpp | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/DevTools/UserspaceEmulator/SoftCPU.cpp b/DevTools/UserspaceEmulator/SoftCPU.cpp index a404d8d1413..567a3cfc229 100644 --- a/DevTools/UserspaceEmulator/SoftCPU.cpp +++ b/DevTools/UserspaceEmulator/SoftCPU.cpp @@ -519,7 +519,21 @@ void SoftCPU::XOR_RM16_imm8(const X86::Instruction&) { TODO(); } void SoftCPU::XOR_RM16_reg16(const X86::Instruction&) { TODO(); } void SoftCPU::XOR_RM32_imm32(const X86::Instruction&) { TODO(); } void SoftCPU::XOR_RM32_imm8(const X86::Instruction&) { TODO(); } -void SoftCPU::XOR_RM32_reg32(const X86::Instruction&) { TODO(); } + +void SoftCPU::XOR_RM32_reg32(const X86::Instruction& insn) +{ + ASSERT(insn.modrm().is_register()); + auto& dest = *m_reg32_table[insn.modrm().register_index()]; + auto src = *m_reg32_table[insn.register_index()]; + dest ^= src; + + set_cf(false); + set_of(false); + set_zf(dest == 0); + set_sf(dest & 0x80000000); + // FIXME: set_pf +} + void SoftCPU::XOR_RM8_imm8(const X86::Instruction&) { TODO(); } void SoftCPU::XOR_RM8_reg8(const X86::Instruction&) { TODO(); } void SoftCPU::XOR_reg16_RM16(const X86::Instruction&) { TODO(); }