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LibX86: Disassemble most FPU instructions starting with D9
Some of these don't just use the REG bits of the mod/rm byte as slashes, but also the R/M bits to have up to 9 different instructions per opcode/slash combination (1 opcode requires that MOD is != 11, the other 8 have MODE == 11). This is done by making the slashes table two levels deep for these cases. Some of this is cosmetic (e.g "FST st0" has no effect already, but its bit pattern gets disassembled as "FNOP"), but for most uses it isn't. FSTENV and FSTCW have an extraordinary 0x9b prefix. This is not yet handled in this patch.
This commit is contained in:
Nico Weber
Andreas Kling
parent
6f12ab3ced
commit
c99a3efc5b
Notes:
sideshowbarker
2024-07-19 04:30:35 +09:00
Author: https://github.com/nico Commit: https://github.com/SerenityOS/serenity/commit/c99a3efc5ba Pull-request: https://github.com/SerenityOS/serenity/pull/2911 Reviewed-by: https://github.com/awesomekling
5 changed files with 209 additions and 13 deletions
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@ -1379,6 +1379,42 @@ void SoftCPU::FSUB_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FSUBR_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FDIV_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FDIVR_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLD_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FXCH(const X86::Instruction&) { TODO(); }
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void SoftCPU::FST_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FNOP(const X86::Instruction&) { TODO(); }
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void SoftCPU::FSTP_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLDENV(const X86::Instruction&) { TODO(); }
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void SoftCPU::FCHS(const X86::Instruction&) { TODO(); }
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void SoftCPU::FABS(const X86::Instruction&) { TODO(); }
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void SoftCPU::FTST(const X86::Instruction&) { TODO(); }
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void SoftCPU::FXAM(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLDCW(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLD1(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLDL2T(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLDL2E(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLDPI(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLDLG2(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLDLN2(const X86::Instruction&) { TODO(); }
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void SoftCPU::FLDZ(const X86::Instruction&) { TODO(); }
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void SoftCPU::FNSTENV(const X86::Instruction&) { TODO(); }
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void SoftCPU::F2XM1(const X86::Instruction&) { TODO(); };
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void SoftCPU::FYL2X(const X86::Instruction&) { TODO(); };
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void SoftCPU::FPTAN(const X86::Instruction&) { TODO(); };
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void SoftCPU::FPATAN(const X86::Instruction&) { TODO(); };
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void SoftCPU::FXTRACT(const X86::Instruction&) { TODO(); };
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void SoftCPU::FPREM1(const X86::Instruction&) { TODO(); };
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void SoftCPU::FDECSTP(const X86::Instruction&) { TODO(); };
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void SoftCPU::FINCSTP(const X86::Instruction&) { TODO(); };
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void SoftCPU::FNSTCW(const X86::Instruction&) { TODO(); };
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void SoftCPU::FPREM(const X86::Instruction&) { TODO(); };
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void SoftCPU::FYL2XP1(const X86::Instruction&) { TODO(); };
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void SoftCPU::FSQRT(const X86::Instruction&) { TODO(); };
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void SoftCPU::FSINCOS(const X86::Instruction&) { TODO(); };
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void SoftCPU::FRNDINT(const X86::Instruction&) { TODO(); };
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void SoftCPU::FSCALE(const X86::Instruction&) { TODO(); };
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void SoftCPU::FSIN(const X86::Instruction&) { TODO(); };
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void SoftCPU::FCOS(const X86::Instruction&) { TODO(); };
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void SoftCPU::FADD_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::FMUL_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::FCOM_RM64(const X86::Instruction&) { TODO(); }
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@ -582,6 +582,42 @@ private:
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virtual void FSUBR_RM32(const X86::Instruction&) override;
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virtual void FDIV_RM32(const X86::Instruction&) override;
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virtual void FDIVR_RM32(const X86::Instruction&) override;
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virtual void FLD_RM32(const X86::Instruction&) override;
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virtual void FXCH(const X86::Instruction&) override;
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virtual void FST_RM32(const X86::Instruction&) override;
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virtual void FNOP(const X86::Instruction&) override;
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virtual void FSTP_RM32(const X86::Instruction&) override;
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virtual void FLDENV(const X86::Instruction&) override;
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virtual void FCHS(const X86::Instruction&) override;
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virtual void FABS(const X86::Instruction&) override;
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virtual void FTST(const X86::Instruction&) override;
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virtual void FXAM(const X86::Instruction&) override;
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virtual void FLDCW(const X86::Instruction&) override;
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virtual void FLD1(const X86::Instruction&) override;
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virtual void FLDL2T(const X86::Instruction&) override;
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virtual void FLDL2E(const X86::Instruction&) override;
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virtual void FLDPI(const X86::Instruction&) override;
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virtual void FLDLG2(const X86::Instruction&) override;
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virtual void FLDLN2(const X86::Instruction&) override;
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virtual void FLDZ(const X86::Instruction&) override;
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virtual void FNSTENV(const X86::Instruction&) override;
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virtual void F2XM1(const X86::Instruction&) override;
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virtual void FYL2X(const X86::Instruction&) override;
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virtual void FPTAN(const X86::Instruction&) override;
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virtual void FPATAN(const X86::Instruction&) override;
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virtual void FXTRACT(const X86::Instruction&) override;
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virtual void FPREM1(const X86::Instruction&) override;
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virtual void FDECSTP(const X86::Instruction&) override;
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virtual void FINCSTP(const X86::Instruction&) override;
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virtual void FNSTCW(const X86::Instruction&) override;
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virtual void FPREM(const X86::Instruction&) override;
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virtual void FYL2XP1(const X86::Instruction&) override;
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virtual void FSQRT(const X86::Instruction&) override;
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virtual void FSINCOS(const X86::Instruction&) override;
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virtual void FRNDINT(const X86::Instruction&) override;
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virtual void FSCALE(const X86::Instruction&) override;
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virtual void FSIN(const X86::Instruction&) override;
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virtual void FCOS(const X86::Instruction&) override;
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virtual void FADD_RM64(const X86::Instruction&) override;
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virtual void FMUL_RM64(const X86::Instruction&) override;
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virtual void FCOM_RM64(const X86::Instruction&) override;
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@ -124,7 +124,6 @@ static void build(InstructionDescriptor* table, u8 op, const char* mnemonic, Ins
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//default:
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case InvalidFormat:
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case MultibyteWithSlash:
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case MultibyteWithSubopcode:
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case InstructionPrefix:
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case __BeginFormatsWithRMByte:
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case OP_RM16_reg16:
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@ -135,6 +134,8 @@ static void build(InstructionDescriptor* table, u8 op, const char* mnemonic, Ins
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case OP_RM8:
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case OP_RM16:
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case OP_RM32:
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case OP_FPU:
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case OP_FPU_reg:
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case OP_FPU_RM32:
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case OP_FPU_RM64:
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case OP_RM8_reg8:
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@ -190,7 +191,7 @@ static void build(InstructionDescriptor* table, u8 op, const char* mnemonic, Ins
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static void build_slash(InstructionDescriptor* table, u8 op, u8 slash, const char* mnemonic, InstructionFormat format, InstructionHandler handler, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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{
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InstructionDescriptor& d = table[op];
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d.handler = handler;
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ASSERT(d.handler == nullptr);
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d.format = MultibyteWithSlash;
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d.has_rm = true;
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if (!d.slashes)
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@ -199,6 +200,27 @@ static void build_slash(InstructionDescriptor* table, u8 op, u8 slash, const cha
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build(d.slashes, slash, mnemonic, format, handler, lock_prefix_allowed);
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}
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static void build_slash_rm(InstructionDescriptor* table, u8 op, u8 slash, u8 rm, const char* mnemonic, InstructionFormat format, InstructionHandler handler, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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{
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ASSERT((rm & 0xc0) == 0xc0);
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ASSERT(((rm >> 3) & 7) == slash);
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InstructionDescriptor& d0 = table[op];
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ASSERT(d0.format == MultibyteWithSlash);
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InstructionDescriptor& d = d0.slashes[slash];
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if (!d.slashes) {
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// Slash/RM instructions are not always dense, so make them all default to the slash instruction.
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d.slashes = new InstructionDescriptor[8];
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for (int i = 0; i < 8; ++i) {
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d.slashes[i] = d;
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d.slashes[i].slashes = nullptr;
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}
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}
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build(d.slashes, rm & 7, mnemonic, format, handler, lock_prefix_allowed);
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}
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static void build_0f(u8 op, const char* mnemonic, InstructionFormat format, InstructionHandler impl, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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{
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build(s_0f_table16, op, mnemonic, format, impl, lock_prefix_allowed);
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@ -259,6 +281,12 @@ static void build_0f_slash(u8 op, u8 slash, const char* mnemonic, InstructionFor
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build_slash(s_0f_table32, op, slash, mnemonic, format, impl, lock_prefix_allowed);
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}
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static void build_slash_rm(u8 op, u8 slash, u8 rm, const char* mnemonic, InstructionFormat format, InstructionHandler impl, IsLockPrefixAllowed lock_prefix_allowed = LockPrefixNotAllowed)
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{
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build_slash_rm(s_table16, op, slash, rm, mnemonic, format, impl, lock_prefix_allowed);
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build_slash_rm(s_table32, op, slash, rm, mnemonic, format, impl, lock_prefix_allowed);
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}
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[[gnu::constructor]] static void build_opcode_tables()
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{
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build(0x00, "ADD", OP_RM8_reg8, &Interpreter::ADD_RM8_reg8, LockPrefixAllowed);
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@ -448,9 +476,49 @@ static void build_0f_slash(u8 op, u8 slash, const char* mnemonic, InstructionFor
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build_slash(0xD8, 6, "FDIV", OP_FPU_RM32, &Interpreter::FDIV_RM32);
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build_slash(0xD8, 7, "FDIVR", OP_FPU_RM32, &Interpreter::FDIVR_RM32);
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build_slash(0xD9, 0, "FLD", OP_FPU_RM32, &Interpreter::FLD_RM32);
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build_slash(0xD9, 1, "FXCH", OP_FPU_reg, &Interpreter::FXCH);
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// FIXME: D9/1 C9 (...but isn't this what D9/1 does naturally, with C9 just being normal R/M?)
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build_slash(0xD9, 2, "FST", OP_FPU_RM32, &Interpreter::FST_RM32);
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build_slash_rm(0xD9, 2, 0xD0, "FNOP", OP_FPU, &Interpreter::FNOP);
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build_slash(0xD9, 3, "FSTP", OP_FPU_RM32, &Interpreter::FSTP_RM32);
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build_slash(0xD9, 4, "FLDENV", OP_FPU_RM32, &Interpreter::FLDENV);
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build_slash_rm(0xD9, 4, 0xE0, "FCHS", OP_FPU, &Interpreter::FCHS);
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build_slash_rm(0xD9, 4, 0xE1, "FABS", OP_FPU, &Interpreter::FABS);
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build_slash_rm(0xD9, 4, 0xE2, "FTST", OP_FPU, &Interpreter::FTST);
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build_slash_rm(0xD9, 4, 0xE3, "FXAM", OP_FPU, &Interpreter::FXAM);
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build_slash(0xD9, 5, "FLDCW", OP_FPU_RM32, &Interpreter::FLDCW);
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build_slash_rm(0xD9, 5, 0xE8, "FLD1", OP_FPU, &Interpreter::FLD1);
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build_slash_rm(0xD9, 5, 0xE9, "FLDL2T", OP_FPU, &Interpreter::FLDL2T);
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build_slash_rm(0xD9, 5, 0xEA, "FLDL2E", OP_FPU, &Interpreter::FLDL2E);
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build_slash_rm(0xD9, 5, 0xEB, "FLDPI", OP_FPU, &Interpreter::FLDPI);
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build_slash_rm(0xD9, 5, 0xEC, "FLDLG2", OP_FPU, &Interpreter::FLDLG2);
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build_slash_rm(0xD9, 5, 0xED, "FLDLN2", OP_FPU, &Interpreter::FLDLN2);
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build_slash_rm(0xD9, 5, 0xEE, "FLDZ", OP_FPU, &Interpreter::FLDZ);
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build_slash(0xD9, 6, "FNSTENV", OP_FPU_RM32, &Interpreter::FNSTENV);
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// FIXME: Extraodinary prefix 0x9B + 0xD9/6: FSTENV
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build_slash_rm(0xD9, 6, 0xF0, "F2XM1", OP_FPU, &Interpreter::F2XM1);
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build_slash_rm(0xD9, 6, 0xF1, "FYL2X", OP_FPU, &Interpreter::FYL2X);
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build_slash_rm(0xD9, 6, 0xF2, "FPTAN", OP_FPU, &Interpreter::FPTAN);
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build_slash_rm(0xD9, 6, 0xF3, "FPATAN", OP_FPU, &Interpreter::FPATAN);
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build_slash_rm(0xD9, 6, 0xF4, "FXTRACT", OP_FPU, &Interpreter::FXTRACT);
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build_slash_rm(0xD9, 6, 0xF5, "FPREM1", OP_FPU, &Interpreter::FPREM1);
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build_slash_rm(0xD9, 6, 0xF6, "FDECSTP", OP_FPU, &Interpreter::FDECSTP);
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build_slash_rm(0xD9, 6, 0xF7, "FINCSTP", OP_FPU, &Interpreter::FINCSTP);
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build_slash(0xD9, 7, "FNSTCW", OP_FPU_RM32, &Interpreter::FNSTCW);
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// FIXME: Extraodinary prefix 0x9B + 0xD9/7: FSTCW
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build_slash_rm(0xD9, 7, 0xF8, "FPREM", OP_FPU, &Interpreter::FPREM);
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build_slash_rm(0xD9, 7, 0xF9, "FYL2XP1", OP_FPU, &Interpreter::FYL2XP1);
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build_slash_rm(0xD9, 7, 0xFA, "FSQRT", OP_FPU, &Interpreter::FSQRT);
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build_slash_rm(0xD9, 7, 0xFB, "FSINCOS", OP_FPU, &Interpreter::FSINCOS);
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build_slash_rm(0xD9, 7, 0xFC, "FRNDINT", OP_FPU, &Interpreter::FRNDINT);
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build_slash_rm(0xD9, 7, 0xFD, "FSCALE", OP_FPU, &Interpreter::FSCALE);
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build_slash_rm(0xD9, 7, 0xFE, "FSIN", OP_FPU, &Interpreter::FSIN);
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build_slash_rm(0xD9, 7, 0xFF, "FCOS", OP_FPU, &Interpreter::FCOS);
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// FIXME
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for (u8 i = 0; i <= 3; ++i)
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build(0xD9 + i, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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build(0xDA, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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build(0xDB, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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build_slash(0xDC, 0, "FADD", OP_FPU_RM64, &Interpreter::FADD_RM64);
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build_slash(0xDC, 1, "FMUL", OP_FPU_RM64, &Interpreter::FMUL_RM64);
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@ -462,8 +530,9 @@ static void build_0f_slash(u8 op, u8 slash, const char* mnemonic, InstructionFor
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build_slash(0xDC, 7, "FDIVR", OP_FPU_RM64, &Interpreter::FDIVR_RM64);
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// FIXME
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for (u8 i = 0; i <= 2; ++i)
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build(0xDD + i, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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build(0xDD, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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build(0xDE, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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build(0xDF, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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build(0xE0, "LOOPNZ", OP_imm8, &Interpreter::LOOPNZ_imm8);
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build(0xE1, "LOOPZ", OP_imm8, &Interpreter::LOOPZ_imm8);
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@ -774,6 +843,12 @@ String MemoryOrRegisterReference::to_string_o32(const Instruction& insn) const
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return String::format("[%s]", to_string(insn).characters());
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}
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String MemoryOrRegisterReference::to_string_fpu_reg() const
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{
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ASSERT(is_register());
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return register_name(reg_fpu());
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}
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String MemoryOrRegisterReference::to_string_fpu32(const Instruction& insn) const
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{
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if (is_register())
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@ -1077,6 +1152,7 @@ String Instruction::to_string_internal(u32 origin, const SymbolProvider* symbol_
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auto append_rm8 = [&] { builder.append(m_modrm.to_string_o8(*this)); };
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auto append_rm16 = [&] { builder.append(m_modrm.to_string_o16(*this)); };
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auto append_rm32 = [&] { builder.append(m_modrm.to_string_o32(*this)); };
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auto append_fpu_reg = [&] { builder.append(m_modrm.to_string_fpu_reg()); };
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auto append_fpu_rm32 = [&] { builder.append(m_modrm.to_string_fpu32(*this)); };
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auto append_fpu_rm64 = [&] { builder.append(m_modrm.to_string_fpu64(*this)); };
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auto append_imm8 = [&] { builder.appendf("%#02x", imm8()); };
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@ -1342,6 +1418,11 @@ String Instruction::to_string_internal(u32 origin, const SymbolProvider* symbol_
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case OP_RM32:
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append_rm32();
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break;
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case OP_FPU:
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break;
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case OP_FPU_reg:
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append_fpu_reg();
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break;
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case OP_FPU_RM32:
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append_fpu_rm32();
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break;
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@ -1515,7 +1596,6 @@ String Instruction::to_string_internal(u32 origin, const SymbolProvider* symbol_
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return mnemonic;
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case InvalidFormat:
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case MultibyteWithSlash:
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case MultibyteWithSubopcode:
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case __BeginFormatsWithRMByte:
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case __EndFormatsWithRMByte:
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return String::format("(!%s)", mnemonic.characters());
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@ -66,7 +66,6 @@ enum IsLockPrefixAllowed {
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enum InstructionFormat {
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InvalidFormat,
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MultibyteWithSlash,
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MultibyteWithSubopcode,
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InstructionPrefix,
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__BeginFormatsWithRMByte,
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@ -82,6 +81,8 @@ enum InstructionFormat {
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OP_RM8,
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OP_RM16,
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OP_RM32,
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OP_FPU,
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OP_FPU_reg,
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OP_FPU_RM32,
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OP_FPU_RM64,
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OP_RM8_reg8,
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@ -179,6 +180,11 @@ struct InstructionDescriptor {
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bool has_rm { false };
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unsigned imm1_bytes { 0 };
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unsigned imm2_bytes { 0 };
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// Addressed by the 3 REG bits in the MOD-REG-R/M byte.
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// Some slash instructions have further subgroups when MOD is 11,
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// in that case the InstructionDescriptors in slashes have themselves
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// a non-null slashes member that's indexed by the three R/M bits.
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InstructionDescriptor* slashes { nullptr };
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unsigned imm1_bytes_for_address_size(bool a32)
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@ -352,6 +358,7 @@ public:
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String to_string_o8(const Instruction&) const;
|
||||
String to_string_o16(const Instruction&) const;
|
||||
String to_string_o32(const Instruction&) const;
|
||||
String to_string_fpu_reg() const;
|
||||
String to_string_fpu32(const Instruction&) const;
|
||||
String to_string_fpu64(const Instruction&) const;
|
||||
String to_string_mm(const Instruction&) const;
|
||||
|
|
@ -864,20 +871,21 @@ ALWAYS_INLINE Instruction::Instruction(InstructionStreamType& stream, bool o32,
|
|||
m_register_index = m_op & 7;
|
||||
}
|
||||
|
||||
bool hasSlash = m_descriptor->format == MultibyteWithSlash;
|
||||
|
||||
if (hasSlash) {
|
||||
bool has_slash = m_descriptor->format == MultibyteWithSlash;
|
||||
if (has_slash) {
|
||||
m_descriptor = &m_descriptor->slashes[slash()];
|
||||
if ((rm() & 0xc0) == 0xc0 && m_descriptor->slashes)
|
||||
m_descriptor = &m_descriptor->slashes[rm() & 7];
|
||||
}
|
||||
|
||||
if (!m_descriptor->mnemonic) {
|
||||
if (has_sub_op()) {
|
||||
if (hasSlash)
|
||||
if (has_slash)
|
||||
fprintf(stderr, "Instruction %02X %02X /%u not understood\n", m_op, m_sub_op, slash());
|
||||
else
|
||||
fprintf(stderr, "Instruction %02X %02X not understood\n", m_op, m_sub_op);
|
||||
} else {
|
||||
if (hasSlash)
|
||||
if (has_slash)
|
||||
fprintf(stderr, "Instruction %02X /%u not understood\n", m_op, slash());
|
||||
else
|
||||
fprintf(stderr, "Instruction %02X not understood\n", m_op);
|
||||
|
|
|
|||
|
|
@ -164,6 +164,42 @@ public:
|
|||
virtual void FSUBR_RM32(const Instruction&) = 0;
|
||||
virtual void FDIV_RM32(const Instruction&) = 0;
|
||||
virtual void FDIVR_RM32(const Instruction&) = 0;
|
||||
virtual void FLD_RM32(const Instruction&) = 0;
|
||||
virtual void FXCH(const Instruction&) = 0;
|
||||
virtual void FST_RM32(const Instruction&) = 0;
|
||||
virtual void FNOP(const Instruction&) = 0;
|
||||
virtual void FSTP_RM32(const Instruction&) = 0;
|
||||
virtual void FLDENV(const Instruction&) = 0;
|
||||
virtual void FCHS(const Instruction&) = 0;
|
||||
virtual void FABS(const Instruction&) = 0;
|
||||
virtual void FTST(const Instruction&) = 0;
|
||||
virtual void FXAM(const Instruction&) = 0;
|
||||
virtual void FLDCW(const Instruction&) = 0;
|
||||
virtual void FLD1(const Instruction&) = 0;
|
||||
virtual void FLDL2T(const Instruction&) = 0;
|
||||
virtual void FLDL2E(const Instruction&) = 0;
|
||||
virtual void FLDPI(const Instruction&) = 0;
|
||||
virtual void FLDLG2(const Instruction&) = 0;
|
||||
virtual void FLDLN2(const Instruction&) = 0;
|
||||
virtual void FLDZ(const Instruction&) = 0;
|
||||
virtual void FNSTENV(const Instruction&) = 0;
|
||||
virtual void F2XM1(const Instruction&) = 0;
|
||||
virtual void FYL2X(const Instruction&) = 0;
|
||||
virtual void FPTAN(const Instruction&) = 0;
|
||||
virtual void FPATAN(const Instruction&) = 0;
|
||||
virtual void FXTRACT(const Instruction&) = 0;
|
||||
virtual void FPREM1(const Instruction&) = 0;
|
||||
virtual void FDECSTP(const Instruction&) = 0;
|
||||
virtual void FINCSTP(const Instruction&) = 0;
|
||||
virtual void FNSTCW(const Instruction&) = 0;
|
||||
virtual void FPREM(const Instruction&) = 0;
|
||||
virtual void FYL2XP1(const Instruction&) = 0;
|
||||
virtual void FSQRT(const Instruction&) = 0;
|
||||
virtual void FSINCOS(const Instruction&) = 0;
|
||||
virtual void FRNDINT(const Instruction&) = 0;
|
||||
virtual void FSCALE(const Instruction&) = 0;
|
||||
virtual void FSIN(const Instruction&) = 0;
|
||||
virtual void FCOS(const Instruction&) = 0;
|
||||
virtual void FADD_RM64(const Instruction&) = 0;
|
||||
virtual void FMUL_RM64(const Instruction&) = 0;
|
||||
virtual void FCOM_RM64(const Instruction&) = 0;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue