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LibX86: Support disassembling a few FPU opcodes better
This commit is contained in:
Nico Weber
Andreas Kling
parent
d8c8820ee9
commit
f6db97b8a9
Notes:
sideshowbarker
2024-07-19 04:37:31 +09:00
Author: https://github.com/nico Commit: https://github.com/SerenityOS/serenity/commit/f6db97b8a91 Pull-request: https://github.com/SerenityOS/serenity/pull/2880
5 changed files with 126 additions and 6 deletions
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@ -1347,6 +1347,22 @@ void SoftCPU::ESCAPE(const X86::Instruction&)
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TODO();
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}
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void SoftCPU::FADD_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FMUL_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FCOM_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FCOMP_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FSUB_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FSUBR_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FDIV_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FDIVR_RM32(const X86::Instruction&) { TODO(); }
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void SoftCPU::FADD_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::FMUL_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::FCOM_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::FCOMP_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::FSUB_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::FSUBR_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::FDIV_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::FDIVR_RM64(const X86::Instruction&) { TODO(); }
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void SoftCPU::HLT(const X86::Instruction&) { TODO(); }
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void SoftCPU::IDIV_RM16(const X86::Instruction& insn)
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@ -574,6 +574,22 @@ private:
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virtual void ENTER16(const X86::Instruction&) override;
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virtual void ENTER32(const X86::Instruction&) override;
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virtual void ESCAPE(const X86::Instruction&) override;
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virtual void FADD_RM32(const X86::Instruction&) override;
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virtual void FMUL_RM32(const X86::Instruction&) override;
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virtual void FCOM_RM32(const X86::Instruction&) override;
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virtual void FCOMP_RM32(const X86::Instruction&) override;
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virtual void FSUB_RM32(const X86::Instruction&) override;
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virtual void FSUBR_RM32(const X86::Instruction&) override;
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virtual void FDIV_RM32(const X86::Instruction&) override;
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virtual void FDIVR_RM32(const X86::Instruction&) override;
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virtual void FADD_RM64(const X86::Instruction&) override;
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virtual void FMUL_RM64(const X86::Instruction&) override;
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virtual void FCOM_RM64(const X86::Instruction&) override;
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virtual void FCOMP_RM64(const X86::Instruction&) override;
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virtual void FSUB_RM64(const X86::Instruction&) override;
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virtual void FSUBR_RM64(const X86::Instruction&) override;
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virtual void FDIV_RM64(const X86::Instruction&) override;
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virtual void FDIVR_RM64(const X86::Instruction&) override;
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virtual void HLT(const X86::Instruction&) override;
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virtual void IDIV_RM16(const X86::Instruction&) override;
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virtual void IDIV_RM32(const X86::Instruction&) override;
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@ -135,6 +135,8 @@ static void build(InstructionDescriptor* table, u8 op, const char* mnemonic, Ins
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case OP_RM8:
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case OP_RM16:
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case OP_RM32:
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case OP_FPU_RM32:
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case OP_FPU_RM64:
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case OP_RM8_reg8:
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case OP_RM32_reg32:
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case OP_reg32_RM32:
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@ -434,9 +436,34 @@ static void build_0f_slash(u8 op, u8 slash, const char* mnemonic, InstructionFor
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build(0xD6, "SALC", OP, &Interpreter::SALC);
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build(0xD7, "XLAT", OP, &Interpreter::XLAT);
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// FIXME: D8-DF == FPU
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for (u8 i = 0; i <= 7; ++i)
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build(0xD8 + i, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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// D8-DF == FPU
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build_slash(0xD8, 0, "FADD", OP_FPU_RM32, &Interpreter::FADD_RM32);
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build_slash(0xD8, 1, "FMUL", OP_FPU_RM32, &Interpreter::FMUL_RM32);
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build_slash(0xD8, 2, "FCOM", OP_FPU_RM32, &Interpreter::FCOM_RM32);
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// FIXME: D8/2 D1 (...but isn't this what D8/2 does naturally, with D1 just being normal R/M?)
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build_slash(0xD8, 3, "FCOMP", OP_FPU_RM32, &Interpreter::FCOMP_RM32);
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// FIXME: D8/3 D9 (...but isn't this what D8/3 does naturally, with D9 just being normal R/M?)
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build_slash(0xD8, 4, "FSUB", OP_FPU_RM32, &Interpreter::FSUB_RM32);
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build_slash(0xD8, 5, "FSUBR", OP_FPU_RM32, &Interpreter::FSUBR_RM32);
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build_slash(0xD8, 6, "FDIV", OP_FPU_RM32, &Interpreter::FDIV_RM32);
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build_slash(0xD8, 7, "FDIVR", OP_FPU_RM32, &Interpreter::FDIVR_RM32);
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// FIXME
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for (u8 i = 0; i <= 3; ++i)
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build(0xD9 + i, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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build_slash(0xDC, 0, "FADD", OP_FPU_RM64, &Interpreter::FADD_RM64);
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build_slash(0xDC, 1, "FMUL", OP_FPU_RM64, &Interpreter::FMUL_RM64);
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build_slash(0xDC, 2, "FCOM", OP_FPU_RM64, &Interpreter::FCOM_RM64);
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build_slash(0xDC, 3, "FCOMP", OP_FPU_RM64, &Interpreter::FCOMP_RM64);
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build_slash(0xDC, 4, "FSUB", OP_FPU_RM64, &Interpreter::FSUB_RM64);
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build_slash(0xDC, 5, "FSUBR", OP_FPU_RM64, &Interpreter::FSUBR_RM64);
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build_slash(0xDC, 6, "FDIV", OP_FPU_RM64, &Interpreter::FDIV_RM64);
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build_slash(0xDC, 7, "FDIVR", OP_FPU_RM64, &Interpreter::FDIVR_RM64);
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// FIXME
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for (u8 i = 0; i <= 2; ++i)
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build(0xDD + i, "FPU?", OP_RM8, &Interpreter::ESCAPE);
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build(0xE0, "LOOPNZ", OP_imm8, &Interpreter::LOOPNZ_imm8);
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build(0xE1, "LOOPZ", OP_imm8, &Interpreter::LOOPZ_imm8);
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@ -707,6 +734,7 @@ static void build_0f_slash(u8 op, u8 slash, const char* mnemonic, InstructionFor
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static const char* register_name(RegisterIndex8);
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static const char* register_name(RegisterIndex16);
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static const char* register_name(RegisterIndex32);
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static const char* register_name(FpuRegisterIndex);
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static const char* register_name(SegmentRegister);
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static const char* register_name(MMXRegisterIndex);
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@ -728,24 +756,38 @@ const char* Instruction::reg32_name() const
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String MemoryOrRegisterReference::to_string_o8(const Instruction& insn) const
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{
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if (is_register())
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return register_name(static_cast<RegisterIndex8>(m_register_index));
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return register_name(reg8());
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return String::format("[%s]", to_string(insn).characters());
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}
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String MemoryOrRegisterReference::to_string_o16(const Instruction& insn) const
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{
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if (is_register())
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return register_name(static_cast<RegisterIndex16>(m_register_index));
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return register_name(reg16());
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return String::format("[%s]", to_string(insn).characters());
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}
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String MemoryOrRegisterReference::to_string_o32(const Instruction& insn) const
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{
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if (is_register())
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return register_name(static_cast<RegisterIndex32>(m_register_index));
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return register_name(reg32());
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return String::format("[%s]", to_string(insn).characters());
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}
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String MemoryOrRegisterReference::to_string_fpu32(const Instruction& insn) const
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{
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if (is_register())
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return register_name(reg_fpu());
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return String::format("dword ptr [%s]", to_string(insn).characters());
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}
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String MemoryOrRegisterReference::to_string_fpu64(const Instruction& insn) const
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{
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if (is_register())
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return register_name(reg_fpu());
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return String::format("qword ptr [%s]", to_string(insn).characters());
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}
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String MemoryOrRegisterReference::to_string_mm(const Instruction& insn) const
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{
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if (is_register())
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@ -1035,6 +1077,8 @@ String Instruction::to_string_internal(u32 origin, const SymbolProvider* symbol_
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auto append_rm8 = [&] { builder.append(m_modrm.to_string_o8(*this)); };
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auto append_rm16 = [&] { builder.append(m_modrm.to_string_o16(*this)); };
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auto append_rm32 = [&] { builder.append(m_modrm.to_string_o32(*this)); };
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auto append_fpu_rm32 = [&] { builder.append(m_modrm.to_string_fpu32(*this)); };
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auto append_fpu_rm64 = [&] { builder.append(m_modrm.to_string_fpu64(*this)); };
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auto append_imm8 = [&] { builder.appendf("%#02x", imm8()); };
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auto append_imm8_2 = [&] { builder.appendf("%#02x", imm8_2()); };
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auto append_imm16 = [&] { builder.appendf("%#04x", imm16()); };
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@ -1298,6 +1342,12 @@ String Instruction::to_string_internal(u32 origin, const SymbolProvider* symbol_
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case OP_RM32:
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append_rm32();
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break;
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case OP_FPU_RM32:
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append_fpu_rm32();
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break;
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case OP_FPU_RM64:
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append_fpu_rm64();
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break;
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case OP_RM8_reg8:
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append_rm8();
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append(", ");
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@ -1505,6 +1555,12 @@ const char* register_name(RegisterIndex32 register_index)
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return names[register_index & 7];
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}
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const char* register_name(FpuRegisterIndex register_index)
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{
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static constexpr const char* names[] = { "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7" };
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return names[register_index & 7];
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}
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const char* register_name(MMXRegisterIndex register_index)
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{
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static constexpr const char* names[] = { "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" };
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@ -82,6 +82,8 @@ enum InstructionFormat {
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OP_RM8,
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OP_RM16,
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OP_RM32,
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OP_FPU_RM32,
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OP_FPU_RM64,
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OP_RM8_reg8,
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OP_RM32_reg32,
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OP_reg32_RM32,
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@ -256,6 +258,17 @@ enum RegisterIndex32 {
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RegisterEDI
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};
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enum FpuRegisterIndex {
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ST0 = 0,
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ST1,
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ST2,
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ST3,
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ST4,
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ST5,
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ST6,
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ST7
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};
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enum MMXRegisterIndex {
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RegisterMM0 = 0,
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RegisterMM1,
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@ -339,6 +352,8 @@ public:
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String to_string_o8(const Instruction&) const;
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String to_string_o16(const Instruction&) const;
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String to_string_o32(const Instruction&) const;
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String to_string_fpu32(const Instruction&) const;
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String to_string_fpu64(const Instruction&) const;
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String to_string_mm(const Instruction&) const;
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bool is_register() const { return m_register_index != 0xffffffff; }
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@ -347,6 +362,7 @@ public:
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RegisterIndex32 reg32() const { return static_cast<RegisterIndex32>(register_index()); }
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RegisterIndex16 reg16() const { return static_cast<RegisterIndex16>(register_index()); }
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RegisterIndex8 reg8() const { return static_cast<RegisterIndex8>(register_index()); }
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FpuRegisterIndex reg_fpu() const { return static_cast<FpuRegisterIndex>(register_index()); }
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template<typename CPU, typename T>
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void write8(CPU&, const Instruction&, T);
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@ -156,6 +156,22 @@ public:
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virtual void ENTER16(const Instruction&) = 0;
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virtual void ENTER32(const Instruction&) = 0;
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virtual void ESCAPE(const Instruction&) = 0;
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virtual void FADD_RM32(const Instruction&) = 0;
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virtual void FMUL_RM32(const Instruction&) = 0;
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virtual void FCOM_RM32(const Instruction&) = 0;
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virtual void FCOMP_RM32(const Instruction&) = 0;
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virtual void FSUB_RM32(const Instruction&) = 0;
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virtual void FSUBR_RM32(const Instruction&) = 0;
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virtual void FDIV_RM32(const Instruction&) = 0;
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virtual void FDIVR_RM32(const Instruction&) = 0;
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virtual void FADD_RM64(const Instruction&) = 0;
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virtual void FMUL_RM64(const Instruction&) = 0;
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virtual void FCOM_RM64(const Instruction&) = 0;
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virtual void FCOMP_RM64(const Instruction&) = 0;
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virtual void FSUB_RM64(const Instruction&) = 0;
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virtual void FSUBR_RM64(const Instruction&) = 0;
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virtual void FDIV_RM64(const Instruction&) = 0;
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virtual void FDIVR_RM64(const Instruction&) = 0;
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virtual void HLT(const Instruction&) = 0;
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virtual void IDIV_RM16(const Instruction&) = 0;
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virtual void IDIV_RM32(const Instruction&) = 0;
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