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e99fafb683
Add a basic NVMe driver support to serenity based on NVMe spec 1.4. The driver can support multiple NVMe drives (subsystems). But in a NVMe drive, the driver can support one controller with multiple namespaces. Each core will get a separate NVMe Queue. As the system lacks MSI support, PIN based interrupts are used for IO. Tested the NVMe support by replacing IDE driver with the NVMe driver :^)
148 lines
3.4 KiB
C
148 lines
3.4 KiB
C
/*
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* Copyright (c) 2021, Pankaj R <pankydev8@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Endian.h>
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#include <AK/Types.h>
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struct NVMeCompletion;
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struct NVMeSubmission;
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struct ControllerRegister {
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u64 cap;
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u32 vs;
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u32 intms;
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u32 intmc;
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u32 cc;
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u32 rsvd1;
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u32 csts;
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u32 nssr;
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u32 aqa;
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u64 asq;
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u64 acq;
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u64 rsvd2[505];
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};
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struct IdentifyNamespace {
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u64 nsze;
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u64 ncap;
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u8 rsdv1[10];
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u8 flbas;
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u8 rsvd2[100];
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u32 lbaf[16];
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u64 rsvd3[488];
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};
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// BAR
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static constexpr u32 BAR_ADDR_MASK = 0xFFFFFFF0;
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// DOORBELL
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static constexpr u32 REG_SQ0TDBL_START = 0x1000;
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static constexpr u32 REG_SQ0TDBL_END = 0x1003;
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static constexpr u8 DBL_REG_SIZE = 8;
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// CAP
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static constexpr u8 CAP_DBL_SHIFT = 32;
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static constexpr u8 CAP_DBL_MASK = 0xf;
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static constexpr u16 MQES(u64 cap)
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{
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return (cap & 0xffff) + 1;
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}
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// CC – Controller Configuration
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static constexpr u8 CC_EN_BIT = 0x0;
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static constexpr u8 CSTS_RDY_BIT = 0x0;
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static constexpr u8 CC_IOSQES_BIT = 16;
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static constexpr u8 CC_IOCQES_BIT = 20;
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static constexpr u16 CC_AQA_MASK = (0xfff);
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static constexpr u16 ACQ_SIZE(u32 x)
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{
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return (x >> 16) & CC_AQA_MASK;
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}
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static constexpr u16 ASQ_SIZE(u32 x)
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{
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return x & CC_AQA_MASK;
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}
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static constexpr u8 CQ_WIDTH = 4; // CQ is 16 bytes(2^4) in size.
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static constexpr u8 SQ_WIDTH = 6; // SQ size is 64 bytes(2^6) in size.
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static constexpr u16 CQ_SIZE(u16 q_depth)
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{
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return q_depth << CQ_WIDTH;
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}
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static constexpr u16 SQ_SIZE(u16 q_depth)
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{
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return q_depth << SQ_WIDTH;
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}
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static constexpr u8 PHASE_TAG(u16 x)
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{
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return x & 0x1;
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}
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static constexpr u16 CQ_STATUS_FIELD_MASK = 0xfffe;
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static constexpr u16 CQ_STATUS_FIELD(u16 x)
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{
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return (x & CQ_STATUS_FIELD_MASK) >> 1;
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}
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static constexpr u16 IO_QUEUE_SIZE = 64; // TODO:Need to be configurable
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// IDENTIFY
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static constexpr u16 NVMe_IDENTIFY_SIZE = 4096;
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static constexpr u8 NVMe_CNS_ID_ACTIVE_NS = 0x2;
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static constexpr u8 NVMe_CNS_ID_NS = 0x0;
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static constexpr u8 FLBA_SIZE_INDEX = 26;
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static constexpr u8 FLBA_SIZE_MASK = 0xf;
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static constexpr u8 LBA_FORMAT_SUPPORT_INDEX = 128;
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static constexpr u32 LBA_SIZE_MASK = 0x00ff0000;
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// OPCODES
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// ADMIN COMMAND SET
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enum AdminCommandOpCode {
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OP_ADMIN_CREATE_COMPLETION_QUEUE = 0x5,
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OP_ADMIN_CREATE_SUBMISSION_QUEUE = 0x1,
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OP_ADMIN_IDENTIFY = 0x6,
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};
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// IO opcodes
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enum IOCommandOpcode {
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OP_NVME_WRITE = 0x1,
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OP_NVME_READ = 0x2
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};
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// FLAGS
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static constexpr u8 QUEUE_PHY_CONTIGUOUS = (1 << 0);
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static constexpr u8 QUEUE_IRQ_ENABLED = (1 << 1);
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struct NVMeCompletion {
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LittleEndian<u32> cmd_spec;
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LittleEndian<u32> res;
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LittleEndian<u16> sq_head; /* how much of this queue may be reclaimed */
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LittleEndian<u16> sq_id; /* submission queue that generated this entry */
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u16 command_id; /* of the command which completed */
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LittleEndian<u16> status; /* did the command fail, and if so, why? */
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};
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struct DataPtr {
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LittleEndian<u64> prp1;
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LittleEndian<u64> prp2;
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};
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struct NVMeSubmission {
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LittleEndian<u8> op;
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LittleEndian<u8> flags;
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LittleEndian<u16> cmdid;
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LittleEndian<u32> nsid;
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LittleEndian<u64> rsvd;
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LittleEndian<u64> meta_ptr;
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struct DataPtr data_ptr;
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LittleEndian<u32> cdw10;
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LittleEndian<u32> cdw11;
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LittleEndian<u32> cdw12;
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LittleEndian<u32> cdw13;
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LittleEndian<u32> cdw14;
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LittleEndian<u32> cdw15;
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};
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