From 03b059c1d501cf30c2144e99a24f74205892eac5 Mon Sep 17 00:00:00 2001
From: Andrew Church <achurch+github@achurch.org>
Date: Mon, 19 Jan 2015 03:18:03 +0900
Subject: [PATCH] Implement the SRR0 register.

---
 rpcs3/Emu/Cell/SPUThread.cpp | 10 +++++++++-
 rpcs3/Emu/Cell/SPUThread.h   |  1 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/rpcs3/Emu/Cell/SPUThread.cpp b/rpcs3/Emu/Cell/SPUThread.cpp
index 5cf09e5f3f..c4cf028f8f 100644
--- a/rpcs3/Emu/Cell/SPUThread.cpp
+++ b/rpcs3/Emu/Cell/SPUThread.cpp
@@ -558,6 +558,8 @@ u32 SPUThread::GetChannelCount(u32 ch)
 
 	switch (ch)
 	{
+	case SPU_WrSRR0:          res = 1; break;
+	case SPU_RdSRR0:          res = 1; break;
 	case SPU_WrOutMbox:       res = SPU.Out_MBox.GetFreeCount(); break;
 	case SPU_WrOutIntrMbox:   res = SPU.Out_IntrMBox.GetFreeCount(); break;
 	case SPU_RdInMbox:        res = SPU.In_MBox.GetCount(); break;
@@ -589,6 +591,9 @@ void SPUThread::WriteChannel(u32 ch, const u128& r)
 
 	switch (ch)
 	{
+	case SPU_WrSRR0:
+		SRR0 = v & 0x3FFFC;  //LSLR & ~3
+		break;
 	case SPU_WrOutIntrMbox:
 	{
 		if (!group) // if RawSPU
@@ -910,6 +915,9 @@ void SPUThread::ReadChannel(u128& r, u32 ch)
 
 	switch (ch)
 	{
+	case SPU_RdSRR0:
+		v = SRR0;
+		break;
 	case SPU_RdInMbox:
 	{
 		while (!SPU.In_MBox.Pop(v) && !Emu.IsStopped())
@@ -1223,4 +1231,4 @@ spu_thread::spu_thread(u32 entry, const std::string& name, u32 stack_size, u32 p
 	thread->SetPrio(prio ? prio : Emu.GetInfo().GetProcParam().primary_prio);
 
 	argc = 0;
-}
\ No newline at end of file
+}
diff --git a/rpcs3/Emu/Cell/SPUThread.h b/rpcs3/Emu/Cell/SPUThread.h
index 9e48359fae..44534f1d12 100644
--- a/rpcs3/Emu/Cell/SPUThread.h
+++ b/rpcs3/Emu/Cell/SPUThread.h
@@ -276,6 +276,7 @@ class SPUThread : public PPCThread
 public:
 	u128 GPR[128]; // General-Purpose Registers
 	SPU_FPSCR FPSCR;
+	u32 SRR0;
 	SPU_SNRConfig_hdr cfg; // Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2)
 
 	u64 R_ADDR; // reservation address