diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h
index d9ec6b4706..d31a197144 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.h
+++ b/rpcs3/Emu/Cell/PPUDisAsm.h
@@ -1034,7 +1034,7 @@ private:
 		
 		Write(fmt::Format("bc [%x:%x:%x:%x:%x], cr%d[%x], 0x%x, %d, %d", bo0, bo1, bo2, bo3, bo4, bi/4, bi%4, bd, aa, lk));
 	}
-	void SC(s32 sc_code)
+	void SC(u32 sc_code)
 	{
 		switch(sc_code)
 		{
@@ -1454,9 +1454,9 @@ private:
 	{
 		DisAsm_R3_OE_RC("mullw", rd, ra, rb, oe, rc);
 	}
-	void DCBTST(u32 th, u32 ra, u32 rb)
+	void DCBTST(u32 ra, u32 rb, u32 th)
 	{
-		DisAsm_R3("dcbtst", th, ra, rb);
+		DisAsm_R3("dcbtst", ra, rb, th);
 	}
 	void STBUX(u32 rs, u32 ra, u32 rb)
 	{
diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index c1bc040877..2a01ca9320 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -500,7 +500,7 @@ namespace PPU_instr
 	/*0x0e9*/bind_instr(g1f_list, MULLD, RD, RA, RB, OE, RC);
 	/*0x0ea*/bind_instr(g1f_list, ADDME, RD, RA, OE, RC);
 	/*0x0eb*/bind_instr(g1f_list, MULLW, RD, RA, RB, OE, RC);
-	/*0x0f6*/bind_instr(g1f_list, DCBTST, TH, RA, RB);
+	/*0x0f6*/bind_instr(g1f_list, DCBTST, RA, RB, TH);
 	/*0x0f7*/bind_instr(g1f_list, STBUX, RS, RA, RB);
 	/*0x10a*/bind_instr(g1f_list, ADD, RD, RA, RB, OE, RC);
 	/*0x116*/bind_instr(g1f_list, DCBT, RA, RB, TH);
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h
index 9284e52c15..ea9d73444a 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter.h
@@ -20,7 +20,7 @@
 #endif
 
 static u64 rotate_mask[64][64];
-void InitRotateMask()
+inline void InitRotateMask()
 {
 	static bool inited = false;
 	if(inited) return;
@@ -34,11 +34,11 @@ void InitRotateMask()
 	inited = true;
 }
 
-u8 rotl8(const u8 x, const u8 n) { return (x << n) | (x >> (8 - n)); }
-u8 rotr8(const u8 x, const u8 n) { return (x >> n) | (x << (8 - n)); }
+inline u8 rotl8(const u8 x, const u8 n) { return (x << n) | (x >> (8 - n)); }
+inline u8 rotr8(const u8 x, const u8 n) { return (x >> n) | (x << (8 - n)); }
 
-u16 rotl16(const u16 x, const u8 n) { return (x << n) | (x >> (16 - n)); }
-u16 rotr16(const u16 x, const u8 n) { return (x >> n) | (x << (16 - n)); }
+inline u16 rotl16(const u16 x, const u8 n) { return (x << n) | (x >> (16 - n)); }
+inline u16 rotr16(const u16 x, const u8 n) { return (x >> n) | (x << (16 - n)); }
 /*
 u32 rotl32(const u32 x, const u8 n) { return (x << n) | (x >> (32 - n)); }
 u32 rotr32(const u32 x, const u8 n) { return (x >> n) | (x << (32 - n)); }
@@ -2088,7 +2088,7 @@ private:
 		}
 		if(lk) CPU.LR = CPU.PC + 4;
 	}
-	void SC(s32 sc_code)
+	void SC(u32 sc_code)
 	{
 		switch(sc_code)
 		{
@@ -2796,7 +2796,7 @@ private:
 		if(rc) CPU.UpdateCR0<s32>(CPU.GPR[rd]);
 		if(oe) UNK("mullwo");
 	}
-	void DCBTST(u32 th, u32 ra, u32 rb)
+	void DCBTST(u32 ra, u32 rb, u32 th)
 	{
 		//UNK("dcbtst", false);
 		_mm_mfence();
diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h
index 3fce7ffaa6..008a07c879 100644
--- a/rpcs3/Emu/Cell/PPUOpcodes.h
+++ b/rpcs3/Emu/Cell/PPUOpcodes.h
@@ -623,7 +623,7 @@ public:
 	virtual void ADDI(u32 rd, u32 ra, s32 simm16) = 0;
 	virtual void ADDIS(u32 rd, u32 ra, s32 simm16) = 0;
 	virtual void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) = 0;
-	virtual void SC(s32 sc_code) = 0;
+	virtual void SC(u32 sc_code) = 0;
 	virtual void B(s32 ll, u32 aa, u32 lk) = 0;
 	virtual void MCRF(u32 crfd, u32 crfs) = 0;
 	virtual void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) = 0;
@@ -706,7 +706,7 @@ public:
 	virtual void SUBFME(u32 rd, u32 ra, u32 oe, bool rc) = 0;
 	virtual void ADDME(u32 rd, u32 ra, u32 oe, bool rc) = 0;
 	virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
-	virtual void DCBTST(u32 th, u32 ra, u32 rb) = 0;
+	virtual void DCBTST(u32 ra, u32 rb, u32 th) = 0;
 	virtual void STBUX(u32 rs, u32 ra, u32 rb) = 0;
 	virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
 	virtual void DCBT(u32 ra, u32 rb, u32 th) = 0;