From 14969cd8d07459f44f51c6290b9e8fd95ec75b87 Mon Sep 17 00:00:00 2001 From: kd-11 Date: Fri, 8 May 2020 09:08:00 +0300 Subject: [PATCH] rsx: Disable SCA writes to output register if vec result flag is set. - Noticed when debugging X-men origins: wolverine which has a bogus SCA op whilst writing vector to output - It makes no sense for both SCA and VEC to both write to the same register in the same instruction as memory ordering becomes an issue --- .../Emu/RSX/Common/Interpreter/VertexInterpreter.glsl | 11 ++++++----- rpcs3/Emu/RSX/Common/VertexProgramDecompiler.cpp | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/rpcs3/Emu/RSX/Common/Interpreter/VertexInterpreter.glsl b/rpcs3/Emu/RSX/Common/Interpreter/VertexInterpreter.glsl index 5e5427c2f4..e41fda1782 100644 --- a/rpcs3/Emu/RSX/Common/Interpreter/VertexInterpreter.glsl +++ b/rpcs3/Emu/RSX/Common/Interpreter/VertexInterpreter.glsl @@ -239,10 +239,14 @@ void write_sca(in float value) if (d3.sca_dst_tmp == 0x3f) { - if (d3.dst != 0x1f) + if (!d0.vec_result) { reg_mov(dest[d3.dst], vec4(value), d3.sca_mask); } + else + { + reg_mov(cc[d0.cond_reg_sel_1], vec4(value), d3.sca_mask); + } } else { @@ -266,10 +270,7 @@ void write_vec(in vec4 value) if (d0.dst_tmp == 0x3f && !d0.vec_result) { - if (d0.cond_update_enable_1) - { - reg_mov(cc[d0.cond_reg_sel_1], value, write_mask); - } + reg_mov(cc[d0.cond_reg_sel_1], value, write_mask); } else { diff --git a/rpcs3/Emu/RSX/Common/VertexProgramDecompiler.cpp b/rpcs3/Emu/RSX/Common/VertexProgramDecompiler.cpp index 4c3c3ce51f..bd5da8c3ba 100644 --- a/rpcs3/Emu/RSX/Common/VertexProgramDecompiler.cpp +++ b/rpcs3/Emu/RSX/Common/VertexProgramDecompiler.cpp @@ -45,7 +45,7 @@ std::string VertexProgramDecompiler::GetDST(bool is_sca) // ARL writes to special integer registers const bool is_address_reg = !is_sca && (d1.vec_opcode == RSX_VEC_OPCODE_ARL); const auto tmp_index = is_sca ? d3.sca_dst_tmp : d0.dst_tmp; - const bool is_result = is_sca ? (tmp_index == 0x3f) : d0.vec_result; + const bool is_result = is_sca ? !d0.vec_result : d0.vec_result; if (is_result) {