diff --git a/rpcs3/Emu/ARMv7/ARMv7Decoder.cpp b/rpcs3/Emu/ARMv7/ARMv7Decoder.cpp
index 8a361014f4..e5a7b4b87f 100644
--- a/rpcs3/Emu/ARMv7/ARMv7Decoder.cpp
+++ b/rpcs3/Emu/ARMv7/ARMv7Decoder.cpp
@@ -44,20 +44,20 @@ const ARMv7_opcode_t ARMv7_opcode_table[] =
 	ARMv7_OP2(0xfe00, 0x1c00, T1, ADD_IMM),
 	ARMv7_OP2(0xf800, 0x3000, T2, ADD_IMM),
 	ARMv7_OP4(0xfbe0, 0x8000, 0xf100, 0x0000, T3, ADD_IMM, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )),
-	ARMv7_OP4(0xfbf0, 0x8000, 0xf200, 0x0000, T4, ADD_IMM),
+	ARMv7_OP4(0xfbf0, 0x8000, 0xf200, 0x0000, T4, ADD_IMM, SKIP_IF( (BF(16, 19) & 13) == 13 )),
 	ARMv7_OP4(0x0fe0, 0x0000, 0x0280, 0x0000, A1, ADD_IMM),
 	ARMv7_OP2(0xfe00, 0x1800, T1, ADD_REG),
 	ARMv7_OP2(0xff00, 0x4400, T2, ADD_REG, SKIP_IF( (c & 0x87) == 0x85 || BF(3, 6) == 13 )),
-	ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG),
+	ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )),
 	ARMv7_OP4(0x0fe0, 0x0010, 0x0080, 0x0000, A1, ADD_REG),
 	ARMv7_OP4(0x0fe0, 0x0090, 0x0080, 0x0010, A1, ADD_RSR),
 	ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI),
 	ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI),
-	ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI),
+	ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI, SKIP_IF( BF(8, 11) == 15 && BT(20) )),
 	ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI),
 	ARMv7_OP4(0x0fef, 0x0000, 0x028d, 0x0000, A1, ADD_SPI),
 	ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR),
-	ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR),
+	ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR, SKIP_IF( BF(3, 6) == 13 )),
 	ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR),
 	ARMv7_OP4(0x0fef, 0x0010, 0x008d, 0x0000, A1, ADD_SPR),
 
diff --git a/rpcs3/Emu/ARMv7/ARMv7Interpreter.cpp b/rpcs3/Emu/ARMv7/ARMv7Interpreter.cpp
index 71d91acad9..954e07dfcc 100644
--- a/rpcs3/Emu/ARMv7/ARMv7Interpreter.cpp
+++ b/rpcs3/Emu/ARMv7/ARMv7Interpreter.cpp
@@ -1355,6 +1355,7 @@ void ARMv7_instrs::LDR_IMM(ARMv7Context& context, const ARMv7Code code, const AR
 		reject((wback && n == t) || (t == 15 && context.ITSTATE), "UNPREDICTABLE");
 		break;
 	}
+	case A1: throw __FUNCTION__;
 	default: throw __FUNCTION__;
 	}
 
@@ -1441,11 +1442,70 @@ void ARMv7_instrs::LDR_REG(ARMv7Context& context, const ARMv7Code code, const AR
 
 void ARMv7_instrs::LDRB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
 {
+	u32 cond, t, n, imm32;
+	bool index, add, wback;
+
 	switch (type)
 	{
+	case T1:
+	{
+		cond = context.ITSTATE.advance();
+		t = (code.data & 0x7);
+		n = (code.data & 0x38) >> 3;
+		imm32 = (code.data & 0x7c0) >> 4;
+		index = true;
+		add = true;
+		wback = false;
+		break;
+	}
+	case T2:
+	{
+		cond = context.ITSTATE.advance();
+		t = (code.data & 0xf000) >> 12;
+		n = (code.data & 0xf0000) >> 16;
+		imm32 = (code.data & 0xfff);
+		index = true;
+		add = true;
+		wback = false;
+
+		reject(t == 15, "PLD");
+		reject(n == 15, "LDRB (literal)");
+		reject(t == 13, "UNPREDICTABLE");
+		break;
+	}
+	case T3:
+	{
+		cond = context.ITSTATE.advance();
+		t = (code.data & 0xf000) >> 12;
+		n = (code.data & 0xf0000) >> 16;
+		imm32 = (code.data & 0xff);
+		index = (code.data & 0x400);
+		add = (code.data & 0x200);
+		wback = (code.data & 0x100);
+
+		reject(t == 15 && index && !add && !wback, "PLD");
+		reject(n == 15, "LDRB (literal)");
+		reject(index && add && !wback, "LDRBT");
+		reject(!index && !wback, "UNDEFINED");
+		reject(t == 13 || t == 15 || (wback && n == t), "UNPREDICTABLE");
+		break;
+	}
 	case A1: throw __FUNCTION__;
 	default: throw __FUNCTION__;
 	}
+
+	if (ConditionPassed(context, cond))
+	{
+		const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32;
+		const u32 addr = index ? offset_addr : context.read_gpr(n);
+
+		context.write_gpr(t, vm::psv::read8(addr));
+
+		if (wback)
+		{
+			context.write_gpr(n, offset_addr);
+		}
+	}
 }
 
 void ARMv7_instrs::LDRB_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
@@ -2999,11 +3059,67 @@ void ARMv7_instrs::STR_REG(ARMv7Context& context, const ARMv7Code code, const AR
 
 void ARMv7_instrs::STRB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
 {
+	u32 cond, t, n, imm32;
+	bool index, add, wback;
+
 	switch (type)
 	{
+	case T1:
+	{
+		cond = context.ITSTATE.advance();
+		t = (code.data & 0x7);
+		n = (code.data & 0x38) >> 3;
+		imm32 = (code.data & 0x7c0) >> 4;
+		index = true;
+		add = true;
+		wback = false;
+		break;
+	}
+	case T2:
+	{
+		cond = context.ITSTATE.advance();
+		t = (code.data & 0xf000) >> 12;
+		n = (code.data & 0xf0000) >> 16;
+		imm32 = (code.data & 0xfff);
+		index = true;
+		add = true;
+		wback = false;
+
+		reject(n == 15, "UNDEFINED");
+		reject(t == 13 || t == 15, "UNPREDICTABLE");
+		break;
+	}
+	case T3:
+	{
+		cond = context.ITSTATE.advance();
+		t = (code.data & 0xf000) >> 12;
+		n = (code.data & 0xf0000) >> 16;
+		imm32 = (code.data & 0xff);
+		index = (code.data & 0x400);
+		add = (code.data & 0x200);
+		wback = (code.data & 0x100);
+
+		reject(index && add && !wback, "STRBT");
+		reject(n == 15 || (!index && !wback), "UNDEFINED");
+		reject(t == 13 || t == 15 || (wback && n == t), "UNPREDICTABLE");
+		break;
+	}
 	case A1: throw __FUNCTION__;
 	default: throw __FUNCTION__;
 	}
+
+	if (ConditionPassed(context, cond))
+	{
+		const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32;
+		const u32 addr = index ? offset_addr : context.read_gpr(n);
+
+		vm::psv::write8(addr, (u8)context.read_gpr(t));
+
+		if (wback)
+		{
+			context.write_gpr(n, offset_addr);
+		}
+	}
 }
 
 void ARMv7_instrs::STRB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type)
diff --git a/rpcs3/Emu/ARMv7/Modules/sceCtrl.cpp b/rpcs3/Emu/ARMv7/Modules/sceCtrl.cpp
index 1f7d65c5df..972bd85d4c 100644
--- a/rpcs3/Emu/ARMv7/Modules/sceCtrl.cpp
+++ b/rpcs3/Emu/ARMv7/Modules/sceCtrl.cpp
@@ -82,4 +82,4 @@ psv_log_base sceCtrl("SceCtrl", []()
 	REG_FUNC(0x15F96FB0, sceCtrlReadBufferNegative);
 	REG_FUNC(0xE9CB69C8, sceCtrlSetRapidFire);
 	REG_FUNC(0xD8294C9C, sceCtrlClearRapidFire);
-});
\ No newline at end of file
+});
diff --git a/rpcs3/Emu/ARMv7/Modules/sceSysmodule.cpp b/rpcs3/Emu/ARMv7/Modules/sceSysmodule.cpp
index 6584de337a..a845595c87 100644
--- a/rpcs3/Emu/ARMv7/Modules/sceSysmodule.cpp
+++ b/rpcs3/Emu/ARMv7/Modules/sceSysmodule.cpp
@@ -6,21 +6,21 @@ extern psv_log_base sceSysmodule;
 
 s32 sceSysmoduleLoadModule(u16 id)
 {
-	sceSysmodule.Todo("sceSysmoduleLoadModule(id=0x%04x)", id);
+	sceSysmodule.Error("sceSysmoduleLoadModule(id=0x%04x) -> SCE_OK", id);
 
 	return SCE_OK; // loading succeeded
 }
 
 s32 sceSysmoduleUnloadModule(u16 id)
 {
-	sceSysmodule.Todo("sceSysmoduleUnloadModule(id=0x%04x)", id);
+	sceSysmodule.Error("sceSysmoduleUnloadModule(id=0x%04x) -> SCE_OK", id);
 
 	return SCE_OK; // unloading succeeded
 }
 
 s32 sceSysmoduleIsLoaded(u16 id)
 {
-	sceSysmodule.Todo("sceSysmoduleIsLoaded(id=0x%04x)", id);
+	sceSysmodule.Error("sceSysmoduleIsLoaded(id=0x%04x) -> SCE_OK", id);
 
 	return SCE_OK; // module is loaded
 }