From 22917084d9181947876d2b99b0e495109014c291 Mon Sep 17 00:00:00 2001 From: JohnHolmesII Date: Sat, 11 May 2019 00:27:39 -0700 Subject: [PATCH] Explcitly mark overflow in various SIMD functions. Doing so silently created warnings. --- rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp | 2 +- rpcs3/Emu/Cell/SPUInterpreter.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp b/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp index e570326a47..c7897d0362 100644 --- a/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp +++ b/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp @@ -2817,7 +2817,7 @@ void spu_recompiler::FSMB(spu_opcode_t op) c->pshufd(va, va, 0xfa); } - c->movdqa(vm, XmmConst(_mm_set_epi8(128, 64, 32, 16, 8, 4, 2, 1, 128, 64, 32, 16, 8, 4, 2, 1))); + c->movdqa(vm, XmmConst(_mm_set_epi8(-128, 64, 32, 16, 8, 4, 2, 1, -128, 64, 32, 16, 8, 4, 2, 1))); c->pand(va, vm); c->pcmpeqb(va, vm); c->movdqa(SPU_OFF_128(gpr, op.rt), va); diff --git a/rpcs3/Emu/Cell/SPUInterpreter.cpp b/rpcs3/Emu/Cell/SPUInterpreter.cpp index 3017f89404..a4b7080610 100644 --- a/rpcs3/Emu/Cell/SPUInterpreter.cpp +++ b/rpcs3/Emu/Cell/SPUInterpreter.cpp @@ -572,7 +572,7 @@ bool spu_interpreter::FSMB(spu_thread& spu, spu_opcode_t op) { const auto vsrc = spu.gpr[op.ra].vi; const auto bits = _mm_shuffle_epi32(_mm_shufflehi_epi16(_mm_unpackhi_epi8(vsrc, vsrc), 0x50), 0xfa); - const auto mask = _mm_set_epi8(128, 64, 32, 16, 8, 4, 2, 1, 128, 64, 32, 16, 8, 4, 2, 1); + const auto mask = _mm_set_epi8(-128, 64, 32, 16, 8, 4, 2, 1, -128, 64, 32, 16, 8, 4, 2, 1); spu.gpr[op.rt].vi = _mm_cmpeq_epi8(_mm_and_si128(bits, mask), mask); return true; } @@ -1429,7 +1429,7 @@ bool spu_interpreter::FSMBI(spu_thread& spu, spu_opcode_t op) { const auto vsrc = _mm_set_epi32(0, 0, 0, op.i16); const auto bits = _mm_shuffle_epi32(_mm_shufflelo_epi16(_mm_unpacklo_epi8(vsrc, vsrc), 0x50), 0x50); - const auto mask = _mm_set_epi8(128, 64, 32, 16, 8, 4, 2, 1, 128, 64, 32, 16, 8, 4, 2, 1); + const auto mask = _mm_set_epi8(-128, 64, 32, 16, 8, 4, 2, 1, -128, 64, 32, 16, 8, 4, 2, 1); spu.gpr[op.rt].vi = _mm_cmpeq_epi8(_mm_and_si128(bits, mask), mask); return true; }