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SPR removed from SPU

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This commit is contained in:
Nekotekina 2014-08-18 02:39:25 +04:00
commit 55ee7065be
3 changed files with 2 additions and 34 deletions
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17
rpcs3/Emu/Cell/SPUInterpreter.h
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@ -61,17 +61,6 @@ private:
void MFSPR(u32 rt, u32 sa) void MFSPR(u32 rt, u32 sa)
{ {
UNIMPLEMENTED(); UNIMPLEMENTED();
//If register is a dummy register (register labeled 0x0)
if(sa == 0x0)
{
CPU.GPR[rt]._u128.hi = 0x0;
CPU.GPR[rt]._u128.lo = 0x0;
}
else
{
CPU.GPR[rt]._u128.hi = CPU.SPR[sa]._u128.hi;
CPU.GPR[rt]._u128.lo = CPU.SPR[sa]._u128.lo;
}
} }
void RDCH(u32 rt, u32 ra) void RDCH(u32 rt, u32 ra)
{ {
@ -267,11 +256,7 @@ private:
} }
void MTSPR(u32 rt, u32 sa) void MTSPR(u32 rt, u32 sa)
{ {
if(sa != 0) UNIMPLEMENTED();
{
CPU.SPR[sa]._u128.hi = CPU.GPR[rt]._u128.hi;
CPU.SPR[sa]._u128.lo = CPU.GPR[rt]._u128.lo;
}
} }
void WRCH(u32 ra, u32 rt) void WRCH(u32 ra, u32 rt)
{ {

16
rpcs3/Emu/Cell/SPURecompiler.h
View file

@ -471,17 +471,6 @@ private:
void MFSPR(u32 rt, u32 sa) void MFSPR(u32 rt, u32 sa)
{ {
UNIMPLEMENTED(); UNIMPLEMENTED();
//If register is a dummy register (register labeled 0x0)
if(sa == 0x0)
{
CPU.GPR[rt]._u128.hi = 0x0;
CPU.GPR[rt]._u128.lo = 0x0;
}
else
{
CPU.GPR[rt]._u128.hi = CPU.SPR[sa]._u128.hi;
CPU.GPR[rt]._u128.lo = CPU.SPR[sa]._u128.lo;
}
} }
void RDCH(u32 rt, u32 ra) void RDCH(u32 rt, u32 ra)
{ {
@ -1098,11 +1087,6 @@ private:
void MTSPR(u32 rt, u32 sa) void MTSPR(u32 rt, u32 sa)
{ {
UNIMPLEMENTED(); UNIMPLEMENTED();
if(sa != 0)
{
CPU.SPR[sa]._u128.hi = CPU.GPR[rt]._u128.hi;
CPU.SPR[sa]._u128.lo = CPU.GPR[rt]._u128.lo;
}
} }
void WRCH(u32 ra, u32 rt) void WRCH(u32 ra, u32 rt)
{ {

3
rpcs3/Emu/Cell/SPUThread.h
View file

@ -310,8 +310,7 @@ union SPU_SNRConfig_hdr
class SPUThread : public PPCThread class SPUThread : public PPCThread
{ {
public: public:
SPU_GPR_hdr GPR[128]; //General-Purpose Register SPU_GPR_hdr GPR[128]; //General-Purpose Registers
SPU_SPR_hdr SPR[128]; //Special-Purpose Registers
//FPSCR FPSCR; //FPSCR FPSCR;
SPU_SNRConfig_hdr cfg; //Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2) SPU_SNRConfig_hdr cfg; //Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2)