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rsx: Minor cleanup

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kd-11 2018-12-12 11:59:23 +03:00 • committed by kd-11
parent 15488eb247
commit 64a8829614
3 changed files with 3 additions and 134 deletions
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4
rpcs3/Emu/RSX/Null/NullGSRender.cpp
View file

@ -17,6 +17,6 @@ bool NullGSRender::do_method(u32 cmd, u32 value)
}
void NullGSRender::end()
{
{
rsx::method_registers.current_draw_clause.end();
}
}

131
rpcs3/Emu/RSX/RSXThread.cpp
View file

@ -44,136 +44,6 @@ namespace rsx
std::function<bool(u32 addr, bool is_writing)> g_access_violation_handler;
thread* g_current_renderer = nullptr;
#pragma optimize("", off)
void run_tests()
{
#if 0
if (0)
{
auto _get_method_name = [](u32 reg) -> std::string
{
if (reg == FIFO::FIFO_DISABLED_COMMAND)
{
return "COMMAND DISABLED";
}
if (reg == FIFO::FIFO_PACKET_BEGIN)
{
return "PACKET BEGIN";
}
return rsx::get_method_name(reg >> 2);
};
auto _dump_commands = [&](const std::vector<FIFO::register_pair>& commands)
{
LOG_ERROR(RSX, "DUMP BEGINS--------------------------------");
for (const auto &cmd : commands)
{
LOG_ERROR(RSX, "%s (0x%x)", _get_method_name(cmd.reg), cmd.value);
}
LOG_ERROR(RSX, "DUMP ENDS--------------------------------");
};
// Test
std::vector<FIFO::register_pair> fake_commands =
{
{ NV4097_SET_TEXTURE_OFFSET << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 1) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 2) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 3) << 2, 0xdeadbeef },
{ NV4097_SET_TEXTURE_CONTROL3 << 2, 0x100000},
{ NV4097_INVALIDATE_VERTEX_FILE << 2, 0 },
{ NV4097_SET_BEGIN_END << 2, 5 },
{ NV4097_DRAW_ARRAYS << 2, 0xff000000 },
{ NV4097_SET_BEGIN_END << 2, 0},
{ NV4097_SET_TEXTURE_OFFSET << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 1) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 2) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 3) << 2, 0xcafebabe },
{ NV4097_SET_TEXTURE_CONTROL3 << 2, 0x100000},
{ NV4097_INVALIDATE_VERTEX_FILE << 2, 0 },
{ NV4097_SET_BEGIN_END << 2, 5 },
{ NV4097_DRAW_ARRAYS << 2, 0xff0000ff },
{ NV4097_SET_BEGIN_END << 2, 0},
{ NV4097_SET_TEXTURE_OFFSET << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 1) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 2) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 3) << 2, 0xdeadbeef },
{ NV4097_SET_TEXTURE_CONTROL3 << 2, 0x100000},
{ NV4097_INVALIDATE_VERTEX_FILE << 2, 0 },
{ NV4097_SET_BEGIN_END << 2, 5 },
{ NV4097_DRAW_ARRAYS << 2, 0xff0001fe },
{ NV4097_SET_BEGIN_END << 2, 0},
{ 0xffffffff, 0 },
{ NV4097_SET_TEXTURE_OFFSET << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 1) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 2) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 3) << 2, 0xcafebabe },
{ NV4097_SET_TEXTURE_CONTROL3 << 2, 0x100000},
{ NV4097_INVALIDATE_VERTEX_FILE << 2, 0 },
{ NV4097_SET_BEGIN_END << 2, 5 },
{ NV4097_DRAW_ARRAYS << 2, 0xff0002fd },
{ NV4097_SET_BEGIN_END << 2, 0},
{ NV4097_SET_TEXTURE_OFFSET << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 1) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 2) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 3) << 2, 0xdeadbeef },
{ NV4097_SET_TEXTURE_CONTROL3 << 2, 0x100000},
{ NV4097_INVALIDATE_VERTEX_FILE << 2, 0 },
{ NV4097_SET_BEGIN_END << 2, 5 },
{ NV4097_DRAW_ARRAYS << 2, 0xff0003fc },
{ NV4097_SET_BEGIN_END << 2, 0},
{ NV4097_SET_TEXTURE_OFFSET << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 1) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 2) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 3) << 2, 0xcafebabe },
{ NV4097_SET_TEXTURE_CONTROL3 << 2, 0x100000},
{ NV4097_INVALIDATE_VERTEX_FILE << 2, 0 },
{ NV4097_SET_BEGIN_END << 2, 5 },
{ NV4097_DRAW_ARRAYS << 2, 0xff0004fb },
{ NV4097_SET_BEGIN_END << 2, 0},
{ NV4097_SET_TEXTURE_OFFSET << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 1) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 2) << 2, 0xdeadbeef },
{ (NV4097_SET_TEXTURE_OFFSET + 3) << 2, 0xdeadbeef },
{ NV4097_SET_TEXTURE_CONTROL3 << 2, 0x100000},
{ NV4097_INVALIDATE_VERTEX_FILE << 2, 0 },
{ NV4097_SET_BEGIN_END << 2, 5 },
{ NV4097_DRAW_ARRAYS << 2, 0xff0005fa },
{ NV4097_SET_BEGIN_END << 2, 0},
{ 0xffffffff, 0xdead },
};
std::vector<u32> fake_registers(16384);
std::fill(fake_registers.begin(), fake_registers.end(), 0u);
FIFO::flattening_pass flattening_pass;
FIFO::reordering_pass reordering_pass;
FIFO::fifo_buffer_info_t info{ 0, fake_commands.size() * 4, /*7*/18, 0 };
flattening_pass.optimize(info, fake_commands, fake_registers.data());
_dump_commands(fake_commands);
reordering_pass.optimize(info, fake_commands, fake_registers.data());
_dump_commands(fake_commands);
LOG_ERROR(RSX, "FINISHED TEST");
}
#endif
}
#pragma optimize("", on)
u32 get_address(u32 offset, u32 location)
{
@ -535,7 +405,6 @@ namespace rsx
void thread::on_task()
{
m_rsx_thread = std::this_thread::get_id();
run_tests();
g_tls_log_prefix = []
{

2
rpcs3/Emu/RSX/RSXThread.h
View file

@ -564,7 +564,7 @@ namespace rsx
// sync
void sync();
void read_barrier(u32 memory_address, u32 memory_range);
virtual void sync_hint(FIFO_hint hint) {}
virtual void sync_hint(FIFO_hint /*hint*/) {}
gsl::span<const gsl::byte> get_raw_index_array(const draw_clause& draw_indexed_clause) const;
gsl::span<const gsl::byte> get_raw_vertex_buffer(const rsx::data_array_format_info&, u32 base_offset, const draw_clause& draw_array_clause) const;