diff --git a/rpcs3/Emu/Cell/SPUDisAsm.h b/rpcs3/Emu/Cell/SPUDisAsm.h
index 8df572bcf6..f32b4a7cf8 100644
--- a/rpcs3/Emu/Cell/SPUDisAsm.h
+++ b/rpcs3/Emu/Cell/SPUDisAsm.h
@@ -93,7 +93,7 @@ private:
 	}
 	void MFSPR(u32 rt, u32 sa)
 	{
-		DisAsm("mfspr", spu_reg_name[rt], spu_reg_name[sa]);   // Are SPR mapped on the GPR or are there 128 additional registers ? Yes, there are also 128 SPR making 256 registers total
+		DisAsm("mfspr", spu_reg_name[rt], spu_reg_name[sa]);
 	}
 	void RDCH(u32 rt, u32 ra)
 	{
diff --git a/rpcs3/Emu/Cell/SPUThread.h b/rpcs3/Emu/Cell/SPUThread.h
index c794817e6b..1b3386bf06 100644
--- a/rpcs3/Emu/Cell/SPUThread.h
+++ b/rpcs3/Emu/Cell/SPUThread.h
@@ -271,25 +271,6 @@ union SPU_GPR_hdr
 	}
 };
 
-union SPU_SPR_hdr
-{
-	u32 _u32[4];
-	u128 _u128;
-	s128 _i128;
-
-	SPU_SPR_hdr() {}
-
-	std::string ToString() const
-	{
-		return fmt::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
-	}
-
-	void Reset()
-	{
-		memset(this, 0, sizeof(*this));
-	}
-};
-
 union SPU_SNRConfig_hdr
 {
 	u64 value;