From cf86056ba97da1f2526f9d02f495af4995db50de Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Wed, 7 May 2014 23:21:45 -0700
Subject: [PATCH 1/7] Update wxWidgets to fix recompile thing in MSVC.

---
 wxWidgets | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wxWidgets b/wxWidgets
index 143b52a764..5a313d2c7c 160000
--- a/wxWidgets
+++ b/wxWidgets
@@ -1 +1 @@
-Subproject commit 143b52a7645b140dff414f332b97f00444332bb9
+Subproject commit 5a313d2c7cec6914721eac46c623fbb4211d3375

From 134e891068ecd8c31509b77f4eee85f22aef4fee Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Wed, 7 May 2014 23:22:03 -0700
Subject: [PATCH 2/7] Fix operand order in DSTST instruction.

No functional change.  Also, switch SC to use a u32 for more typesafe
opcode decoding - also no functional change.
---
 rpcs3/Emu/Cell/PPUDisAsm.h      |  6 +++---
 rpcs3/Emu/Cell/PPUInstrTable.h  |  2 +-
 rpcs3/Emu/Cell/PPUInterpreter.h | 14 +++++++-------
 rpcs3/Emu/Cell/PPUOpcodes.h     |  4 ++--
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h
index d9ec6b4706..d31a197144 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.h
+++ b/rpcs3/Emu/Cell/PPUDisAsm.h
@@ -1034,7 +1034,7 @@ private:
 		
 		Write(fmt::Format("bc [%x:%x:%x:%x:%x], cr%d[%x], 0x%x, %d, %d", bo0, bo1, bo2, bo3, bo4, bi/4, bi%4, bd, aa, lk));
 	}
-	void SC(s32 sc_code)
+	void SC(u32 sc_code)
 	{
 		switch(sc_code)
 		{
@@ -1454,9 +1454,9 @@ private:
 	{
 		DisAsm_R3_OE_RC("mullw", rd, ra, rb, oe, rc);
 	}
-	void DCBTST(u32 th, u32 ra, u32 rb)
+	void DCBTST(u32 ra, u32 rb, u32 th)
 	{
-		DisAsm_R3("dcbtst", th, ra, rb);
+		DisAsm_R3("dcbtst", ra, rb, th);
 	}
 	void STBUX(u32 rs, u32 ra, u32 rb)
 	{
diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index c1bc040877..2a01ca9320 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -500,7 +500,7 @@ namespace PPU_instr
 	/*0x0e9*/bind_instr(g1f_list, MULLD, RD, RA, RB, OE, RC);
 	/*0x0ea*/bind_instr(g1f_list, ADDME, RD, RA, OE, RC);
 	/*0x0eb*/bind_instr(g1f_list, MULLW, RD, RA, RB, OE, RC);
-	/*0x0f6*/bind_instr(g1f_list, DCBTST, TH, RA, RB);
+	/*0x0f6*/bind_instr(g1f_list, DCBTST, RA, RB, TH);
 	/*0x0f7*/bind_instr(g1f_list, STBUX, RS, RA, RB);
 	/*0x10a*/bind_instr(g1f_list, ADD, RD, RA, RB, OE, RC);
 	/*0x116*/bind_instr(g1f_list, DCBT, RA, RB, TH);
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h
index 9284e52c15..ea9d73444a 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter.h
@@ -20,7 +20,7 @@
 #endif
 
 static u64 rotate_mask[64][64];
-void InitRotateMask()
+inline void InitRotateMask()
 {
 	static bool inited = false;
 	if(inited) return;
@@ -34,11 +34,11 @@ void InitRotateMask()
 	inited = true;
 }
 
-u8 rotl8(const u8 x, const u8 n) { return (x << n) | (x >> (8 - n)); }
-u8 rotr8(const u8 x, const u8 n) { return (x >> n) | (x << (8 - n)); }
+inline u8 rotl8(const u8 x, const u8 n) { return (x << n) | (x >> (8 - n)); }
+inline u8 rotr8(const u8 x, const u8 n) { return (x >> n) | (x << (8 - n)); }
 
-u16 rotl16(const u16 x, const u8 n) { return (x << n) | (x >> (16 - n)); }
-u16 rotr16(const u16 x, const u8 n) { return (x >> n) | (x << (16 - n)); }
+inline u16 rotl16(const u16 x, const u8 n) { return (x << n) | (x >> (16 - n)); }
+inline u16 rotr16(const u16 x, const u8 n) { return (x >> n) | (x << (16 - n)); }
 /*
 u32 rotl32(const u32 x, const u8 n) { return (x << n) | (x >> (32 - n)); }
 u32 rotr32(const u32 x, const u8 n) { return (x >> n) | (x << (32 - n)); }
@@ -2088,7 +2088,7 @@ private:
 		}
 		if(lk) CPU.LR = CPU.PC + 4;
 	}
-	void SC(s32 sc_code)
+	void SC(u32 sc_code)
 	{
 		switch(sc_code)
 		{
@@ -2796,7 +2796,7 @@ private:
 		if(rc) CPU.UpdateCR0<s32>(CPU.GPR[rd]);
 		if(oe) UNK("mullwo");
 	}
-	void DCBTST(u32 th, u32 ra, u32 rb)
+	void DCBTST(u32 ra, u32 rb, u32 th)
 	{
 		//UNK("dcbtst", false);
 		_mm_mfence();
diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h
index 3fce7ffaa6..008a07c879 100644
--- a/rpcs3/Emu/Cell/PPUOpcodes.h
+++ b/rpcs3/Emu/Cell/PPUOpcodes.h
@@ -623,7 +623,7 @@ public:
 	virtual void ADDI(u32 rd, u32 ra, s32 simm16) = 0;
 	virtual void ADDIS(u32 rd, u32 ra, s32 simm16) = 0;
 	virtual void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) = 0;
-	virtual void SC(s32 sc_code) = 0;
+	virtual void SC(u32 sc_code) = 0;
 	virtual void B(s32 ll, u32 aa, u32 lk) = 0;
 	virtual void MCRF(u32 crfd, u32 crfs) = 0;
 	virtual void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) = 0;
@@ -706,7 +706,7 @@ public:
 	virtual void SUBFME(u32 rd, u32 ra, u32 oe, bool rc) = 0;
 	virtual void ADDME(u32 rd, u32 ra, u32 oe, bool rc) = 0;
 	virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
-	virtual void DCBTST(u32 th, u32 ra, u32 rb) = 0;
+	virtual void DCBTST(u32 ra, u32 rb, u32 th) = 0;
 	virtual void STBUX(u32 rs, u32 ra, u32 rb) = 0;
 	virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
 	virtual void DCBT(u32 ra, u32 rb, u32 th) = 0;

From d54237b0a36656be4cce574b32ca95eb90909fe9 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Wed, 7 May 2014 23:23:23 -0700
Subject: [PATCH 3/7] Fix SRAWI instruction decoding.

It's SH, not sh.  Lowercase combines bits from two fields.
---
 rpcs3/Emu/Cell/PPUInstrTable.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index 2a01ca9320..5ce51768a1 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -547,7 +547,7 @@ namespace PPU_instr
 	/*0x296*/bind_instr(g1f_list, STWBRX, RS, RA, RB);
 	/*0x297*/bind_instr(g1f_list, STFSX, FRS, RA, RB);
 	/*0x2a7*/bind_instr(g1f_list, STVRX, VS, RA, RB);
-	/*0x2d5*/bind_instr(g1f_list, STSWI, RD, RA, NB);
+	/*0x2d5*/bind_instr(g1f_list, STSWI, RS, RA, NB);
 	/*0x2d7*/bind_instr(g1f_list, STFDX, FRS, RA, RB);
 	/*0x307*/bind_instr(g1f_list, LVLXL, VD, RA, RB);
 	/*0x316*/bind_instr(g1f_list, LHBRX, RD, RA, RB);
@@ -555,7 +555,7 @@ namespace PPU_instr
 	/*0x31a*/bind_instr(g1f_list, SRAD, RA, RS, RB, RC);
 	/*0x327*/bind_instr(g1f_list, LVRXL, VD, RA, RB);
 	/*0x336*/bind_instr(g1f_list, DSS, STRM, L_6);
-	/*0x338*/bind_instr(g1f_list, SRAWI, RA, RS, sh, RC);
+	/*0x338*/bind_instr(g1f_list, SRAWI, RA, RS, SH, RC);
 	/*0x33a*/bind_instr(g1f_list, SRADI1, RA, RS, sh, RC);
 	/*0x33b*/bind_instr(g1f_list, SRADI2, RA, RS, sh, RC);
 	/*0x356*/bind_instr(g1f_list, EIEIO);

From a5c18b2a09861e279b75bf0204cd36ab58a7b82e Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Wed, 7 May 2014 23:28:34 -0700
Subject: [PATCH 4/7] Add missing TD instruction.

---
 rpcs3/Emu/Cell/PPUDisAsm.h      | 4 ++++
 rpcs3/Emu/Cell/PPUInstrTable.h  | 1 +
 rpcs3/Emu/Cell/PPUInterpreter.h | 4 ++++
 rpcs3/Emu/Cell/PPUOpcodes.h     | 2 ++
 4 files changed, 11 insertions(+)

diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h
index d31a197144..8fe80c47aa 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.h
+++ b/rpcs3/Emu/Cell/PPUDisAsm.h
@@ -1320,6 +1320,10 @@ private:
 	{
 		DisAsm_R3_RC("andc", ra, rs, rb, rc);
 	}
+	void TD(u32 to, u32 ra, u32 rb)
+	{
+		DisAsm_INT1_R2("td", to, ra, rb);
+	}
 	void LVEWX(u32 vd, u32 ra, u32 rb)
 	{
 		DisAsm_V1_R2("lvewx", vd, ra, rb);
diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index 5ce51768a1..a01c16fe3a 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -470,6 +470,7 @@ namespace PPU_instr
 	/*0x037*/bind_instr(g1f_list, LWZUX, RD, RA, RB);
 	/*0x03a*/bind_instr(g1f_list, CNTLZD, RA, RS, RC);
 	/*0x03c*/bind_instr(g1f_list, ANDC, RA, RS, RB, RC);
+	/*0x03c*/bind_instr(g1f_list, TD, TO, RA, RB);
 	/*0x047*/bind_instr(g1f_list, LVEWX, VD, RA, RB);
 	/*0x049*/bind_instr(g1f_list, MULHD, RD, RA, RB, RC);
 	/*0x04b*/bind_instr(g1f_list, MULHW, RD, RA, RB, RC);
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h
index ea9d73444a..209cdafd14 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter.h
@@ -2518,6 +2518,10 @@ private:
 		CPU.GPR[ra] = CPU.GPR[rs] & ~CPU.GPR[rb];
 		if(rc) CPU.UpdateCR0<s64>(CPU.GPR[ra]);
 	}
+	void TD(u32 to, u32 ra, u32 rb)
+	{
+		UNK("td");
+	}
 	void LVEWX(u32 vd, u32 ra, u32 rb)
 	{
 		//const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL;
diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h
index 008a07c879..223f7a9eef 100644
--- a/rpcs3/Emu/Cell/PPUOpcodes.h
+++ b/rpcs3/Emu/Cell/PPUOpcodes.h
@@ -280,6 +280,7 @@ namespace PPU_opcodes
 		LWZUX  = 0x037,
 		CNTLZD = 0x03a,
 		ANDC   = 0x03c,
+		TD     = 0x044,
 		LVEWX  = 0x047, //Load Vector Element Word Indexed
 		MULHD  = 0x049,
 		MULHW  = 0x04b,
@@ -676,6 +677,7 @@ public:
 	virtual void LWZUX(u32 rd, u32 ra, u32 rb) = 0;
 	virtual void CNTLZD(u32 ra, u32 rs, bool rc) = 0;
 	virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) = 0;
+	virtual void TD(u32 to, u32 ra, u32 rb) = 0;
 	virtual void LVEWX(u32 vd, u32 ra, u32 rb) = 0;
 	virtual void MULHD(u32 rd, u32 ra, u32 rb, bool rc) = 0;
 	virtual void MULHW(u32 rd, u32 ra, u32 rb, bool rc) = 0;

From 592e13b6a049265a981b90f2fc1e4b8b104ec9d9 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Wed, 7 May 2014 23:37:30 -0700
Subject: [PATCH 5/7] Add missing LSWX and STSWX instructions.

---
 rpcs3/Emu/Cell/PPUDisAsm.h      | 8 ++++++++
 rpcs3/Emu/Cell/PPUInstrTable.h  | 2 ++
 rpcs3/Emu/Cell/PPUInterpreter.h | 8 ++++++++
 rpcs3/Emu/Cell/PPUOpcodes.h     | 4 ++++
 4 files changed, 22 insertions(+)

diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h
index 8fe80c47aa..cc5a05ce27 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.h
+++ b/rpcs3/Emu/Cell/PPUDisAsm.h
@@ -1629,6 +1629,10 @@ private:
 	{
 		DisAsm_R3("ldbrx", rd, ra, rb);
 	}
+	void LSWX(u32 rd, u32 ra, u32 rb)
+	{
+		DisAsm_R3("lswx", rd, ra, rb);
+	}
 	void LWBRX(u32 rd, u32 ra, u32 rb)
 	{
 		DisAsm_R3("lwbrx", rd, ra, rb);
@@ -1673,6 +1677,10 @@ private:
 	{
 		DisAsm_V1_R2("stvlx", vs, ra, rb);
 	}
+	void STSWX(u32 rs, u32 ra, u32 rb)
+	{
+		DisAsm_R3("swswx", rs, ra, rb);
+	}
 	void STWBRX(u32 rs, u32 ra, u32 rb)
 	{
 		DisAsm_R3("stwbrx", rs, ra, rb);
diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index a01c16fe3a..2ebd93e99e 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -534,6 +534,7 @@ namespace PPU_instr
 	/*0x1eb*/bind_instr(g1f_list, DIVW, RD, RA, RB, OE, RC);
 	/*0x207*/bind_instr(g1f_list, LVLX, VD, RA, RB);
 	/*0x214*/bind_instr(g1f_list, LDBRX, RD, RA, RB);
+	/*0x215*/bind_instr(g1f_list, LSWX, RD, RA, RB);
 	/*0x216*/bind_instr(g1f_list, LWBRX, RD, RA, RB);
 	/*0x217*/bind_instr(g1f_list, LFSX, FRD, RA, RB);
 	/*0x218*/bind_instr(g1f_list, SRW, RA, RS, RB, RC);
@@ -545,6 +546,7 @@ namespace PPU_instr
 	/*0x257*/bind_instr(g1f_list, LFDX, FRD, RA, RB);
 	/*0x277*/bind_instr(g1f_list, LFDUX, FRD, RA, RB);
 	/*0x287*/bind_instr(g1f_list, STVLX, VS, RA, RB);
+	/*0x296*/bind_instr(g1f_list, STSWX, RS, RA, RB);
 	/*0x296*/bind_instr(g1f_list, STWBRX, RS, RA, RB);
 	/*0x297*/bind_instr(g1f_list, STFSX, FRS, RA, RB);
 	/*0x2a7*/bind_instr(g1f_list, STVRX, VS, RA, RB);
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h
index 209cdafd14..c228309a97 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter.h
@@ -3016,6 +3016,10 @@ private:
 	{
 		CPU.GPR[rd] = (u64&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]];
 	}
+	void LSWX(u32 rd, u32 ra, u32 rb)
+	{
+		UNK("lswx");
+	}
 	void LWBRX(u32 rd, u32 ra, u32 rb)
 	{
 		CPU.GPR[rd] = (u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]];
@@ -3106,6 +3110,10 @@ private:
 
 		Memory.WriteLeft(addr, 16 - eb, CPU.VPR[vs]._u8 + eb);
 	}
+	void STSWX(u32 rs, u32 ra, u32 rb)
+	{
+		UNK("stwsx");
+	}
 	void STWBRX(u32 rs, u32 ra, u32 rb)
 	{
 		(u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]] = CPU.GPR[rs];
diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h
index 223f7a9eef..485de7dbfc 100644
--- a/rpcs3/Emu/Cell/PPUOpcodes.h
+++ b/rpcs3/Emu/Cell/PPUOpcodes.h
@@ -345,6 +345,7 @@ namespace PPU_opcodes
 		DIVW   = 0x1eb,
 		LVLX   = 0x207, //Load Vector Left Indexed
 		LDBRX  = 0x214,
+		LSWX   = 0x215,
 		LWBRX  = 0x216,
 		LFSX   = 0x217,
 		SRW    = 0x218,
@@ -356,6 +357,7 @@ namespace PPU_opcodes
 		LFDX   = 0x257,
 		LFDUX  = 0x277,
 		STVLX  = 0x287, //Store Vector Left Indexed
+		STSWX  = 0x295,
 		STWBRX = 0x296,
 		STFSX  = 0x297,
 		STVRX  = 0x2a7, //Store Vector Right Indexed
@@ -741,6 +743,7 @@ public:
 	virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
 	virtual void LVLX(u32 vd, u32 ra, u32 rb) = 0;
 	virtual void LDBRX(u32 rd, u32 ra, u32 rb) = 0;
+	virtual void LSWX(u32 rd, u32 ra, u32 rb) = 0;
 	virtual void LWBRX(u32 rd, u32 ra, u32 rb) = 0;
 	virtual void LFSX(u32 frd, u32 ra, u32 rb) = 0;
 	virtual void SRW(u32 ra, u32 rs, u32 rb, bool rc) = 0;
@@ -752,6 +755,7 @@ public:
 	virtual void LFDX(u32 frd, u32 ra, u32 rb) = 0;
 	virtual void LFDUX(u32 frd, u32 ra, u32 rb) = 0;
 	virtual void STVLX(u32 vs, u32 ra, u32 rb) = 0;
+	virtual void STSWX(u32 rs, u32 ra, u32 rb) = 0;
 	virtual void STWBRX(u32 rs, u32 ra, u32 rb) = 0;
 	virtual void STFSX(u32 frs, u32 ra, u32 rb) = 0;
 	virtual void STVRX(u32 vs, u32 ra, u32 rb) = 0;

From 9290453d2e206ee5a198daba1138a94a611d89fb Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Wed, 7 May 2014 23:48:27 -0700
Subject: [PATCH 6/7] Add missing STFSUX/STFDUX instructions.

---
 rpcs3/Emu/Cell/PPUDisAsm.h      |  8 ++++++++
 rpcs3/Emu/Cell/PPUInstrTable.h  |  2 ++
 rpcs3/Emu/Cell/PPUInterpreter.h | 12 ++++++++++++
 rpcs3/Emu/Cell/PPUOpcodes.h     |  4 ++++
 4 files changed, 26 insertions(+)

diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h
index cc5a05ce27..be33460752 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.h
+++ b/rpcs3/Emu/Cell/PPUDisAsm.h
@@ -1693,6 +1693,10 @@ private:
 	{
 		DisAsm_V1_R2("stvrx", sd, ra, rb);
 	}
+	void STFSUX(u32 frs, u32 ra, u32 rb)
+	{
+		DisAsm_F1_R2("stfsux", frs, ra, rb);
+	}
 	void STSWI(u32 rd, u32 ra, u32 nb)
 	{
 		DisAsm_R2_INT1("stswi", rd, ra, nb);
@@ -1701,6 +1705,10 @@ private:
 	{
 		DisAsm_F1_R2("stfdx", frs, ra, rb);
 	}
+	void STFDUX(u32 frs, u32 ra, u32 rb)
+	{
+		DisAsm_F1_R2("stfdux", frs, ra, rb);
+	}
 	void LVLXL(u32 vd, u32 ra, u32 rb)
 	{
 		DisAsm_V1_R2("lvlxl", vd, ra, rb);
diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index 2ebd93e99e..27463ce2ab 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -550,8 +550,10 @@ namespace PPU_instr
 	/*0x296*/bind_instr(g1f_list, STWBRX, RS, RA, RB);
 	/*0x297*/bind_instr(g1f_list, STFSX, FRS, RA, RB);
 	/*0x2a7*/bind_instr(g1f_list, STVRX, VS, RA, RB);
+	/*0x2b7*/bind_instr(g1f_list, STFSUX, FRS, RA, RB);
 	/*0x2d5*/bind_instr(g1f_list, STSWI, RS, RA, NB);
 	/*0x2d7*/bind_instr(g1f_list, STFDX, FRS, RA, RB);
+	/*0x2d7*/bind_instr(g1f_list, STFDUX, FRS, RA, RB);
 	/*0x307*/bind_instr(g1f_list, LVLXL, VD, RA, RB);
 	/*0x316*/bind_instr(g1f_list, LHBRX, RD, RA, RB);
 	/*0x318*/bind_instr(g1f_list, SRAW, RA, RS, RB, RC);
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h
index c228309a97..8dd160d0b3 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter.h
@@ -3129,6 +3129,12 @@ private:
 
 		Memory.WriteRight(addr - eb, eb, CPU.VPR[vs]._u8);
 	}
+	void STFSUX(u32 frs, u32 ra, u32 rb)
+	{
+		const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
+		Memory.Write32(addr, CPU.FPR[frs].To32());
+		CPU.GPR[ra] = addr;
+	}
 	void STSWI(u32 rd, u32 ra, u32 nb)
 	{
 			u64 EA = ra ? CPU.GPR[ra] : 0;
@@ -3161,6 +3167,12 @@ private:
 	{
 		Memory.Write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u64&)CPU.FPR[frs]);
 	}
+	void STFDUX(u32 frs, u32 ra, u32 rb)
+	{
+		const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
+		Memory.Write64(addr, (u64&)CPU.FPR[frs]);
+		CPU.GPR[ra] = addr;
+	}
 	void LVLXL(u32 vd, u32 ra, u32 rb)
 	{
 		const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h
index 485de7dbfc..af5fd6623b 100644
--- a/rpcs3/Emu/Cell/PPUOpcodes.h
+++ b/rpcs3/Emu/Cell/PPUOpcodes.h
@@ -361,8 +361,10 @@ namespace PPU_opcodes
 		STWBRX = 0x296,
 		STFSX  = 0x297,
 		STVRX  = 0x2a7, //Store Vector Right Indexed
+		STFSUX = 0x2b7,
 		STSWI  = 0x2d5,
 		STFDX  = 0x2d7, //Store Floating-Point Double Indexed
+		STFDUX = 0x2f7,
 		LVLXL  = 0x307, //Load Vector Left Indexed Last
 		LHBRX  = 0x316,
 		SRAW   = 0x318,
@@ -759,8 +761,10 @@ public:
 	virtual void STWBRX(u32 rs, u32 ra, u32 rb) = 0;
 	virtual void STFSX(u32 frs, u32 ra, u32 rb) = 0;
 	virtual void STVRX(u32 vs, u32 ra, u32 rb) = 0;
+	virtual void STFSUX(u32 frs, u32 ra, u32 rb) = 0;
 	virtual void STSWI(u32 rd, u32 ra, u32 nb) = 0;
 	virtual void STFDX(u32 frs, u32 ra, u32 rb) = 0;
+	virtual void STFDUX(u32 frs, u32 ra, u32 rb) = 0;
 	virtual void LVLXL(u32 vd, u32 ra, u32 rb) = 0;
 	virtual void LHBRX(u32 rd, u32 ra, u32 rb) = 0;
 	virtual void SRAW(u32 ra, u32 rs, u32 rb, bool rc) = 0;

From ff89e06fd6afc9a18450e593e10db4c55bb34a7f Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Wed, 7 May 2014 23:53:19 -0700
Subject: [PATCH 7/7] Add missing ICBI instruction.

---
 rpcs3/Emu/Cell/PPUDisAsm.h      | 5 ++++-
 rpcs3/Emu/Cell/PPUInstrTable.h  | 2 +-
 rpcs3/Emu/Cell/PPUInterpreter.h | 5 ++++-
 rpcs3/Emu/Cell/PPUOpcodes.h     | 2 +-
 4 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h
index be33460752..8682e3564d 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.h
+++ b/rpcs3/Emu/Cell/PPUDisAsm.h
@@ -1784,7 +1784,10 @@ private:
 	{
 		DisAsm_R2_RC("extsw", ra, rs, rc);
 	}
-	/*0x3d6*///ICBI
+	void ICBI(u32 ra, u32 rb)
+	{
+		DisAsm_R2("icbi", ra, rb);
+	}
 	void DCBZ(u32 ra, u32 rs)
 	{
 		DisAsm_R2("dcbz", ra, rs);
diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index 27463ce2ab..8962eb7376 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -571,7 +571,7 @@ namespace PPU_instr
 	/*0x3ba*/bind_instr(g1f_list, EXTSB, RA, RS, RC);
 	/*0x3d7*/bind_instr(g1f_list, STFIWX, FRS, RA, RB);
 	/*0x3da*/bind_instr(g1f_list, EXTSW, RA, RS, RC);
-	/*0x3d6*///ICBI
+	/*0x3d6*/bind_instr(g1f_list, ICBI, RA, RB);
 	/*0x3f6*/bind_instr(g1f_list, DCBZ, RA, RB);
 
 	bind_instr(g3a_list, LD, RD, RA, DS);
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h
index 8dd160d0b3..421f7603a4 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter.h
@@ -3291,7 +3291,10 @@ private:
 		//CPU.XER.CA = ((s64)CPU.GPR[ra] < 0); // ???
 		if(rc) CPU.UpdateCR0<s32>(CPU.GPR[ra]);
 	}
-	/*0x3d6*///ICBI
+	void ICBI(u32 ra, u32 rs)
+	{
+		// Clear jit for the specified block?  Nothing to do in the interpreter.
+	}
 	void DCBZ(u32 ra, u32 rs)
 	{
 		//UNK("dcbz", false);
diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h
index af5fd6623b..ec96bac715 100644
--- a/rpcs3/Emu/Cell/PPUOpcodes.h
+++ b/rpcs3/Emu/Cell/PPUOpcodes.h
@@ -782,7 +782,7 @@ public:
 	virtual void EXTSB(u32 ra, u32 rs, bool rc) = 0;
 	virtual void STFIWX(u32 frs, u32 ra, u32 rb) = 0;
 	virtual void EXTSW(u32 ra, u32 rs, bool rc) = 0;
-	//ICBI
+	virtual void ICBI(u32 ra, u32 rb) = 0;
 	virtual void DCBZ(u32 ra, u32 rb) = 0;
 	virtual void LWZ(u32 rd, u32 ra, s32 d) = 0;
 	virtual void LWZU(u32 rd, u32 ra, s32 d) = 0;