diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h
index cc5a05ce27..be33460752 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.h
+++ b/rpcs3/Emu/Cell/PPUDisAsm.h
@@ -1693,6 +1693,10 @@ private:
 	{
 		DisAsm_V1_R2("stvrx", sd, ra, rb);
 	}
+	void STFSUX(u32 frs, u32 ra, u32 rb)
+	{
+		DisAsm_F1_R2("stfsux", frs, ra, rb);
+	}
 	void STSWI(u32 rd, u32 ra, u32 nb)
 	{
 		DisAsm_R2_INT1("stswi", rd, ra, nb);
@@ -1701,6 +1705,10 @@ private:
 	{
 		DisAsm_F1_R2("stfdx", frs, ra, rb);
 	}
+	void STFDUX(u32 frs, u32 ra, u32 rb)
+	{
+		DisAsm_F1_R2("stfdux", frs, ra, rb);
+	}
 	void LVLXL(u32 vd, u32 ra, u32 rb)
 	{
 		DisAsm_V1_R2("lvlxl", vd, ra, rb);
diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index 2ebd93e99e..27463ce2ab 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -550,8 +550,10 @@ namespace PPU_instr
 	/*0x296*/bind_instr(g1f_list, STWBRX, RS, RA, RB);
 	/*0x297*/bind_instr(g1f_list, STFSX, FRS, RA, RB);
 	/*0x2a7*/bind_instr(g1f_list, STVRX, VS, RA, RB);
+	/*0x2b7*/bind_instr(g1f_list, STFSUX, FRS, RA, RB);
 	/*0x2d5*/bind_instr(g1f_list, STSWI, RS, RA, NB);
 	/*0x2d7*/bind_instr(g1f_list, STFDX, FRS, RA, RB);
+	/*0x2d7*/bind_instr(g1f_list, STFDUX, FRS, RA, RB);
 	/*0x307*/bind_instr(g1f_list, LVLXL, VD, RA, RB);
 	/*0x316*/bind_instr(g1f_list, LHBRX, RD, RA, RB);
 	/*0x318*/bind_instr(g1f_list, SRAW, RA, RS, RB, RC);
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h
index c228309a97..8dd160d0b3 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter.h
@@ -3129,6 +3129,12 @@ private:
 
 		Memory.WriteRight(addr - eb, eb, CPU.VPR[vs]._u8);
 	}
+	void STFSUX(u32 frs, u32 ra, u32 rb)
+	{
+		const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
+		Memory.Write32(addr, CPU.FPR[frs].To32());
+		CPU.GPR[ra] = addr;
+	}
 	void STSWI(u32 rd, u32 ra, u32 nb)
 	{
 			u64 EA = ra ? CPU.GPR[ra] : 0;
@@ -3161,6 +3167,12 @@ private:
 	{
 		Memory.Write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u64&)CPU.FPR[frs]);
 	}
+	void STFDUX(u32 frs, u32 ra, u32 rb)
+	{
+		const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
+		Memory.Write64(addr, (u64&)CPU.FPR[frs]);
+		CPU.GPR[ra] = addr;
+	}
 	void LVLXL(u32 vd, u32 ra, u32 rb)
 	{
 		const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h
index 485de7dbfc..af5fd6623b 100644
--- a/rpcs3/Emu/Cell/PPUOpcodes.h
+++ b/rpcs3/Emu/Cell/PPUOpcodes.h
@@ -361,8 +361,10 @@ namespace PPU_opcodes
 		STWBRX = 0x296,
 		STFSX  = 0x297,
 		STVRX  = 0x2a7, //Store Vector Right Indexed
+		STFSUX = 0x2b7,
 		STSWI  = 0x2d5,
 		STFDX  = 0x2d7, //Store Floating-Point Double Indexed
+		STFDUX = 0x2f7,
 		LVLXL  = 0x307, //Load Vector Left Indexed Last
 		LHBRX  = 0x316,
 		SRAW   = 0x318,
@@ -759,8 +761,10 @@ public:
 	virtual void STWBRX(u32 rs, u32 ra, u32 rb) = 0;
 	virtual void STFSX(u32 frs, u32 ra, u32 rb) = 0;
 	virtual void STVRX(u32 vs, u32 ra, u32 rb) = 0;
+	virtual void STFSUX(u32 frs, u32 ra, u32 rb) = 0;
 	virtual void STSWI(u32 rd, u32 ra, u32 nb) = 0;
 	virtual void STFDX(u32 frs, u32 ra, u32 rb) = 0;
+	virtual void STFDUX(u32 frs, u32 ra, u32 rb) = 0;
 	virtual void LVLXL(u32 vd, u32 ra, u32 rb) = 0;
 	virtual void LHBRX(u32 rd, u32 ra, u32 rb) = 0;
 	virtual void SRAW(u32 ra, u32 rs, u32 rb, bool rc) = 0;