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Merge pull request #887 from gopalsr83/master
PPU: Corrected SC instruction format to comply with the PowerISA
This commit is contained in:
commit
937214bc59
8 changed files with 28 additions and 30 deletions
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@ -1030,14 +1030,13 @@ private:
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Write(fmt::Format("bc [%x:%x:%x:%x:%x], cr%d[%x], 0x%x, %d, %d", bo0, bo1, bo2, bo3, bo4, bi/4, bi%4, bd, aa, lk));
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}
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void SC(u32 sc_code)
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void SC(u32 lev)
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{
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switch(sc_code)
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switch (lev)
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{
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case 0x1: Write("HyperCall"); break;
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case 0x2: Write("sc"); break;
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case 0x22: Write("HyperCall LV1"); break;
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default: Write(fmt::Format("Unknown sc: 0x%x", sc_code));
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case 0x0: Write("sc"); break;
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case 0x1: Write("HyperCall LV1"); break;
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default: Write(fmt::Format("Unknown sc: 0x%x", lev));
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}
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}
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void B(s32 ll, u32 aa, u32 lk)
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@ -162,8 +162,8 @@ namespace PPU_instr
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//This field mask is used to identify the CR fields that are to be updated by the mtcrf instruction.
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static CodeField<12, 19> CRM;
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//
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static CodeField<6, 31> SYS;
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// This field is used to identify the system call level
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static CodeField<20, 26> LEV;
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//Immediate field specifying a 16-bit signed two's complement integer that is sign-extended to 64 bits
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static CodeFieldSigned<16, 31> D;
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@ -238,7 +238,7 @@ namespace PPU_instr
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bind_instr(main_list, ADDI, RD, RA, simm16);
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bind_instr(main_list, ADDIS, RD, RA, simm16);
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bind_instr(main_list, BC, BO, BI, BD, AA, LK);
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bind_instr(main_list, SC, SYS);
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bind_instr(main_list, SC, LEV);
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bind_instr(main_list, B, LI, AA, LK);
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bind_instr(main_list, RLWIMI, RA, RS, SH, MB, ME, RC);
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bind_instr(main_list, RLWINM, RA, RS, SH, MB, ME, RC);
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@ -2164,13 +2164,13 @@ private:
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if(lk) CPU.LR = nextLR;
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}
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}
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void SC(u32 sc_code)
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void SC(u32 lev)
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{
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switch(sc_code)
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switch (lev)
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{
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case 0x1: UNK(fmt::Format("HyperCall %d", CPU.GPR[0])); break;
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case 0x2: SysCall(); break;
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case 0x3:
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case 0x0: SysCall(); break;
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case 0x1: UNK("HyperCall LV1"); break;
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case 0x2:
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Emu.GetSFuncManager().StaticExecute(CPU, (u32)CPU.GPR[11]);
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if (Ini.HLELogging.GetValue())
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{
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@ -2178,9 +2178,8 @@ private:
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Emu.GetSFuncManager()[CPU.GPR[11]]->name, CPU.GPR[3], CPU.PC);
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}
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break;
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case 0x4: CPU.FastStop(); break;
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case 0x22: UNK("HyperCall LV1"); break;
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default: UNK(fmt::Format("Unknown sc: 0x%x", sc_code));
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case 0x3: CPU.FastStop(); break;
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default: UNK(fmt::Format("Unknown sc: 0x%x", lev)); break;
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}
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}
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void B(s32 ll, u32 aa, u32 lk)
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@ -1995,20 +1995,20 @@ void Compiler::BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) {
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CreateBranch(CheckBranchCondition(bo, bi), target_i32, lk ? true : false);
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}
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void Compiler::SC(u32 sc_code) {
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switch (sc_code) {
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case 2:
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void Compiler::SC(u32 lev) {
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switch (lev) {
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case 0:
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Call<void>("SysCalls.DoSyscall", SysCalls::DoSyscall, m_state.args[CompileTaskState::Args::State], GetGpr(11));
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break;
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case 3:
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case 2:
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Call<void>("StaticFuncManager.StaticExecute", &StaticFuncManager::StaticExecute,
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m_ir_builder->getInt64((u64)&Emu.GetSFuncManager()), m_state.args[CompileTaskState::Args::State], GetGpr(11, 32));
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break;
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case 4:
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case 3:
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Call<void>("PPUThread.FastStop", &PPUThread::FastStop, m_state.args[CompileTaskState::Args::State]);
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break;
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default:
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CompilationError(fmt::Format("SC %u", sc_code));
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CompilationError(fmt::Format("SC %u", lev));
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break;
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}
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}
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@ -628,7 +628,7 @@ public:
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virtual void ADDI(u32 rd, u32 ra, s32 simm16) = 0;
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virtual void ADDIS(u32 rd, u32 ra, s32 simm16) = 0;
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virtual void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) = 0;
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virtual void SC(u32 sc_code) = 0;
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virtual void SC(u32 lev) = 0;
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virtual void B(s32 ll, u32 aa, u32 lk) = 0;
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virtual void MCRF(u32 crfd, u32 crfs) = 0;
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virtual void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) = 0;
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@ -188,7 +188,7 @@ void fix_import(Module* module, u32 func, u32 addr)
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*ptr++ = ORI(11, 11, func & 0xffff);
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*ptr++ = NOP();
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++ptr;
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*ptr++ = SC(2);
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*ptr++ = SC(0);
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*ptr++ = BLR();
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*ptr++ = NOP();
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*ptr++ = NOP();
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@ -85,7 +85,7 @@ void StaticFuncManager::StaticAnalyse(void* ptr, u32 size, u32 base)
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LOG_NOTICE(LOADER, "Function '%s' hooked (addr=0x%x)", m_static_funcs_list[j]->name, i * 4 + base);
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m_static_funcs_list[j]->found++;
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data[i+0] = re32(0x39600000 | j); // li r11, j
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data[i+1] = se32(0x44000003); // sc 3
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data[i+1] = se32(0x44000042); // sc 2
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data[i+2] = se32(0x4e800020); // blr
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i += 2; // skip modified code
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}
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@ -343,17 +343,17 @@ namespace loader
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Emu.SetRSXCallback(rsx_callback_data.addr());
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rsx_callback_data[0] = ADDI(r11, 0, 0x3ff);
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rsx_callback_data[1] = SC(2);
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rsx_callback_data[1] = SC(0);
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rsx_callback_data[2] = BLR();
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auto ppu_thr_exit_data = vm::ptr<u32>::make(Memory.MainMem.AllocAlign(3 * 4));
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ppu_thr_exit_data[0] = ADDI(r11, 0, 41);
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ppu_thr_exit_data[1] = SC(2);
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ppu_thr_exit_data[1] = SC(0);
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ppu_thr_exit_data[2] = BLR();
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Emu.SetCPUThreadExit(ppu_thr_exit_data.addr());
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auto ppu_thr_stop_data = vm::ptr<u32>::make(Memory.MainMem.AllocAlign(2 * 4));
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ppu_thr_stop_data[0] = SC(4);
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ppu_thr_stop_data[0] = SC(3);
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ppu_thr_stop_data[1] = BLR();
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Emu.SetCPUThreadStop(ppu_thr_stop_data.addr());
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@ -493,7 +493,7 @@ namespace loader
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static const stub_data =
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{
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be_t<u32>::make(MR(11, 2)),
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be_t<u32>::make(SC(2)),
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be_t<u32>::make(SC(0)),
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be_t<u32>::make(BLR())
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};
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