mirror of
https://github.com/RPCS3/rpcs3.git
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spu: implement assembly functions for arm64
This commit is contained in:
sguo35
Ivan
parent
77ab872bec
commit
9e57efe82c
2 changed files with 330 additions and 13 deletions
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@ -36,17 +36,9 @@ const extern spu_decoder<spu_iname> g_spu_iname;
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const extern spu_decoder<spu_iflag> g_spu_iflag;
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// Move 4 args for calling native function from a GHC calling convention function
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#if defined(ARCH_X64)
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static u8* move_args_ghc_to_native(u8* raw)
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{
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#ifdef ARCH_ARM64
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// Note: this is a placeholder to get rpcs3 working for now
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// mov x0, x22
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// mov x1, x23
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// mov x2, x24
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// mov x3, x25
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std::memcpy(raw, "\xE0\x03\x16\xAA\xE1\x03\x17\xAA\xE2\x03\x18\xAA\xE3\x03\x19\xAA", 16);
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return raw + 16;
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#else
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#ifdef _WIN32
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// mov rcx, r13
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// mov rdx, rbp
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@ -62,14 +54,34 @@ static u8* move_args_ghc_to_native(u8* raw)
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#endif
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return raw + 12;
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#endif
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}
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#elif defined(ARCH_ARM64)
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static void ghc_cpp_trampoline(u64 fn_target, native_asm& c, auto& args)
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{
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using namespace asmjit;
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Label target = c.newLabel();
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c.mov(args[0], a64::x19);
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c.mov(args[1], a64::x20);
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c.mov(args[2], a64::x21);
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c.mov(args[3], a64::x22);
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c.ldr(a64::x15, arm::Mem(target));
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c.br(a64::x15);
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c.brk(Imm(0x42)); // Unreachable
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c.bind(target);
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c.embedUInt64(fn_target);
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}
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#endif
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DECLARE(spu_runtime::tr_dispatch) = []
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{
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#ifdef __APPLE__
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pthread_jit_write_protect_np(false);
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#endif
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#if defined(ARCH_X64)
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// Generate a special trampoline to spu_recompiler_base::dispatch with pause instruction
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u8* const trptr = jit_runtime::alloc(32, 16);
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u8* raw = move_args_ghc_to_native(trptr);
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@ -81,10 +93,24 @@ DECLARE(spu_runtime::tr_dispatch) = []
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const u64 target = reinterpret_cast<u64>(&spu_recompiler_base::dispatch);
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std::memcpy(raw + 4, &target, 8);
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return reinterpret_cast<spu_function_t>(trptr);
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#elif defined(ARCH_ARM64)
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auto trptr = build_function_asm<spu_function_t>("tr_dispatch",
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[](native_asm& c, auto& args)
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{
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c.yield();
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ghc_cpp_trampoline(reinterpret_cast<u64>(&spu_recompiler_base::dispatch), c, args);
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c.embed("tr_dispatch", 11);
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});
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return trptr;
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#else
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#error "Unimplemented"
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#endif
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}();
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DECLARE(spu_runtime::tr_branch) = []
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{
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#if defined(ARCH_X64)
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// Generate a trampoline to spu_recompiler_base::branch
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u8* const trptr = jit_runtime::alloc(32, 16);
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u8* raw = move_args_ghc_to_native(trptr);
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@ -94,10 +120,24 @@ DECLARE(spu_runtime::tr_branch) = []
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const u64 target = reinterpret_cast<u64>(&spu_recompiler_base::branch);
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std::memcpy(raw + 4, &target, 8);
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return reinterpret_cast<spu_function_t>(trptr);
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#elif defined(ARCH_ARM64)
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auto trptr = build_function_asm<spu_function_t>("tr_branch",
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[](native_asm& c, auto& args)
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{
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ghc_cpp_trampoline(reinterpret_cast<u64>(&spu_recompiler_base::branch), c, args);
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c.embed("tr_branch", 9);
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});
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return trptr;
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#else
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#error "Unimplemented"
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#endif
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}();
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DECLARE(spu_runtime::tr_interpreter) = []
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{
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#if defined(ARCH_X64)
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u8* const trptr = jit_runtime::alloc(32, 16);
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u8* raw = move_args_ghc_to_native(trptr);
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*raw++ = 0xff; // jmp [rip]
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@ -106,6 +146,16 @@ DECLARE(spu_runtime::tr_interpreter) = []
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const u64 target = reinterpret_cast<u64>(&spu_recompiler_base::old_interpreter);
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std::memcpy(raw + 4, &target, 8);
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return reinterpret_cast<spu_function_t>(trptr);
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#elif defined(ARCH_ARM64)
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auto trptr = build_function_asm<spu_function_t>("tr_interpreter",
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[](native_asm& c, auto& args)
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{
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ghc_cpp_trampoline(reinterpret_cast<u64>(&spu_recompiler_base::old_interpreter), c, args);
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c.embed("tr_interpreter", 14);
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});
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return trptr;
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#endif
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}();
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DECLARE(spu_runtime::g_dispatcher) = []
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@ -123,6 +173,7 @@ DECLARE(spu_runtime::g_dispatcher) = []
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DECLARE(spu_runtime::tr_all) = []
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{
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#if defined(ARCH_X64)
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u8* const trptr = jit_runtime::alloc(32, 16);
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u8* raw = trptr;
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@ -172,6 +223,53 @@ DECLARE(spu_runtime::tr_all) = []
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*raw++ = 0xc2;
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return reinterpret_cast<spu_function_t>(trptr);
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#elif defined(ARCH_ARM64)
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auto trptr = build_function_asm<spu_function_t>("tr_all",
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[](native_asm& c, auto& args)
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{
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using namespace asmjit;
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// w1: PC (eax in x86 SPU)
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// x7: lsa (rcx in x86 SPU)
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// Load PC
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Label pc_offset = c.newLabel();
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c.ldr(a64::x0, arm::Mem(pc_offset));
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c.ldr(a64::w1, arm::Mem(a64::x19, a64::x0)); // REG_Base + offset(spu_thread::pc)
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// Compute LS address = REG_Sp + PC, store into x7 (use later)
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c.add(a64::x7, a64::x20, a64::x1);
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// Load 32b from LS address
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c.ldr(a64::w3, arm::Mem(a64::x7));
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// shr (32 - 20)
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c.lsr(a64::w3, a64::w3, Imm(32 - 20));
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// Load g_dispatcher
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Label g_dispatcher_offset = c.newLabel();
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c.ldr(a64::x4, arm::Mem(g_dispatcher_offset));
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// Update block hash
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Label block_hash_offset = c.newLabel();
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c.mov(a64::x5, Imm(0));
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c.ldr(a64::x6, arm::Mem(block_hash_offset));
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c.str(a64::x5, arm::Mem(a64::x19, a64::x6)); // REG_Base + offset(spu_thread::block_hash)
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// Jump to [g_dispatcher + idx * 8]
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c.mov(a64::x6, Imm(8));
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c.mul(a64::x6, a64::x3, a64::x6);
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c.add(a64::x4, a64::x4, a64::x6);
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c.ldr(a64::x4, arm::Mem(a64::x4));
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c.br(a64::x4);
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c.bind(pc_offset);
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c.embedUInt64(::offset32(&spu_thread::pc));
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c.bind(g_dispatcher_offset);
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c.embedUInt64(reinterpret_cast<u64>(g_dispatcher));
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c.bind(block_hash_offset);
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c.embedUInt64(::offset32(&spu_thread::block_hash));
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c.embed("tr_all", 6);
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});
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return trptr;
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#else
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#error "Unimplemented"
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#endif
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}();
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DECLARE(spu_runtime::g_gateway) = build_function_asm<spu_function_t>("spu_gateway", [](native_asm& c, auto& args)
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@ -262,8 +360,69 @@ DECLARE(spu_runtime::g_gateway) = build_function_asm<spu_function_t>("spu_gatewa
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#endif
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c.ret();
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#else
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#elif defined(ARCH_ARM64)
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// Push callee saved registers to the stack
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// We need to save x18-x30 = 13 x 8B each + 8 bytes for 16B alignment = 112B
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c.sub(a64::sp, a64::sp, Imm(112));
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c.stp(a64::x18, a64::x19, arm::Mem(a64::sp));
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c.stp(a64::x20, a64::x21, arm::Mem(a64::sp, 16));
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c.stp(a64::x22, a64::x23, arm::Mem(a64::sp, 32));
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c.stp(a64::x24, a64::x25, arm::Mem(a64::sp, 48));
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c.stp(a64::x26, a64::x27, arm::Mem(a64::sp, 64));
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c.stp(a64::x28, a64::x29, arm::Mem(a64::sp, 80));
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c.str(a64::x30, arm::Mem(a64::sp, 96));
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// Save native stack pointer for longjmp emulation
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Label sp_offset = c.newLabel();
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c.ldr(a64::x26, arm::Mem(sp_offset));
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// sp not allowed to be used in load/stores directly
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c.mov(a64::x15, a64::sp);
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c.str(a64::x15, arm::Mem(args[0], a64::x26));
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// Move 4 args (despite spu_function_t def)
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c.mov(a64::x19, args[0]);
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c.mov(a64::x20, args[1]);
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c.mov(a64::x21, args[2]);
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c.mov(a64::x22, args[3]);
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// Save ret address to stack
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// since non-tail calls to cpp fns may corrupt lr and
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// g_tail_escape may jump out of a fn before the epilogue can restore lr
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Label ret_addr = c.newLabel();
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c.adr(a64::x0, ret_addr);
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c.str(a64::x0, arm::Mem(a64::sp, 104));
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Label call_target = c.newLabel();
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c.ldr(a64::x0, arm::Mem(call_target));
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c.blr(a64::x0);
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c.bind(ret_addr);
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// Restore stack ptr
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c.ldr(a64::x26, arm::Mem(sp_offset));
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c.ldr(a64::x15, arm::Mem(a64::x19, a64::x26));
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c.mov(a64::sp, a64::x15);
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// Restore registers from the stack
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c.ldp(a64::x18, a64::x19, arm::Mem(a64::sp));
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c.ldp(a64::x20, a64::x21, arm::Mem(a64::sp, 16));
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c.ldp(a64::x22, a64::x23, arm::Mem(a64::sp, 32));
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c.ldp(a64::x24, a64::x25, arm::Mem(a64::sp, 48));
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c.ldp(a64::x26, a64::x27, arm::Mem(a64::sp, 64));
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c.ldp(a64::x28, a64::x29, arm::Mem(a64::sp, 80));
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c.ldr(a64::x30, arm::Mem(a64::sp, 96));
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// Restore stack ptr
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c.add(a64::sp, a64::sp, Imm(112));
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// Return
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c.ret(a64::x30);
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c.bind(sp_offset);
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c.embedUInt64(::offset32(&spu_thread::saved_native_sp));
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c.bind(call_target);
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c.embedUInt64(reinterpret_cast<u64>(spu_runtime::tr_all));
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c.embed("spu_gateway", 11);
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#else
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#error "Unimplemented"
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#endif
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});
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@ -278,6 +437,22 @@ DECLARE(spu_runtime::g_escape) = build_function_asm<void(*)(spu_thread*)>("spu_e
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// Return to the return location
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c.sub(x86::rsp, 8);
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c.ret();
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#elif defined(ARCH_ARM64)
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// Restore native stack pointer (longjmp emulation)
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Label sp_offset = c.newLabel();
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c.ldr(a64::x15, arm::Mem(sp_offset));
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c.ldr(a64::x15, arm::Mem(args[0], a64::x15));
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c.mov(a64::sp, a64::x15);
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c.ldr(a64::x30, arm::Mem(a64::sp, 104));
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c.ret(a64::x30);
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c.bind(sp_offset);
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c.embedUInt64(::offset32(&spu_thread::saved_native_sp));
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c.embed("spu_escape", 10);
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#else
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#error "Unimplemented"
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#endif
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});
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@ -299,6 +474,35 @@ DECLARE(spu_runtime::g_tail_escape) = build_function_asm<void(*)(spu_thread*, sp
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c.xor_(x86::ebx, x86::ebx);
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c.mov(x86::qword_ptr(x86::rsp), args[1]);
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c.ret();
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#elif defined(ARCH_ARM64)
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// Restore native stack pointer (longjmp emulation)
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Label sp_offset = c.newLabel();
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c.ldr(a64::x15, arm::Mem(sp_offset));
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c.ldr(a64::x15, arm::Mem(args[0], a64::x15));
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c.mov(a64::sp, a64::x15);
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// Reload lr, since it might've been clobbered by a cpp fn
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// and g_tail_escape runs before epilogue
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c.ldr(a64::x30, arm::Mem(a64::sp, 104));
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// Tail call, GHC CC
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c.mov(a64::x19, args[0]); // REG_Base
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Label ls_offset = c.newLabel();
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c.ldr(a64::x20, arm::Mem(ls_offset));
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c.ldr(a64::x20, arm::Mem(args[0], a64::x20)); // REG_Sp
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c.mov(a64::x21, args[2]); // REG_Hp
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c.eor(a64::w22, a64::w22, a64::w22); // REG_R1
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c.br(args[1]);
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c.bind(ls_offset);
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c.embedUInt64(::offset32(&spu_thread::ls));
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c.bind(sp_offset);
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c.embedUInt64(::offset32(&spu_thread::saved_native_sp));
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c.embed("spu_tail_escape", 15);
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#else
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#error "Unimplemented"
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#endif
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});
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@ -1157,6 +1361,7 @@ spu_function_t spu_runtime::find(const u32* ls, u32 addr) const
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spu_function_t spu_runtime::make_branch_patchpoint(u16 data) const
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{
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#if defined(ARCH_X64)
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u8* const raw = jit_runtime::alloc(16, 16);
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if (!raw)
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@ -1185,6 +1390,33 @@ spu_function_t spu_runtime::make_branch_patchpoint(u16 data) const
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raw[15] = data & 0xff;
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return reinterpret_cast<spu_function_t>(raw);
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#elif defined(ARCH_ARM64)
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spu_function_t func = build_function_asm<spu_function_t>("", [&](native_asm& c, auto& args)
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{
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using namespace asmjit;
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// Save the jmp addr to GHC CC 3rd arg -> REG_Hp
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Label replace_addr = c.newLabel();
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c.adr(a64::x21, replace_addr);
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Label branch_target = c.newLabel();
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c.bind(replace_addr);
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c.ldr(a64::x9, arm::Mem(branch_target));
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c.br(a64::x9);
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c.bind(branch_target);
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c.embedUInt64(reinterpret_cast<u64>(tr_branch));
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c.embedUInt8(data >> 8);
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c.embedUInt8(data & 0xff);
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c.embed("branch_patchpoint", 17);
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});
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return func;
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#else
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#error "Unimplemented"
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#endif
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}
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spu_recompiler_base::spu_recompiler_base()
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@ -1200,6 +1432,7 @@ void spu_recompiler_base::dispatch(spu_thread& spu, void*, u8* rip)
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// If code verification failed from a patched patchpoint, clear it with a dispatcher jump
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if (rip)
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{
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#if defined(ARCH_X64)
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const s64 rel = reinterpret_cast<u64>(spu_runtime::tr_all) - reinterpret_cast<u64>(rip - 8) - 5;
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union
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@ -1215,6 +1448,34 @@ void spu_recompiler_base::dispatch(spu_thread& spu, void*, u8* rip)
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bytes[7] = 0x90;
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atomic_storage<u64>::release(*reinterpret_cast<u64*>(rip - 8), result);
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#elif defined(ARCH_ARM64)
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auto jump_instrs = build_function_asm<spu_function_t>("", [](native_asm& c, auto& args)
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{
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using namespace asmjit;
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Label branch_target = c.newLabel();
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c.ldr(a64::x9, arm::Mem(branch_target)); // PC rel load
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c.br(a64::x9);
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c.bind(branch_target);
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c.embedUInt64(reinterpret_cast<u64>(spu_runtime::tr_all));
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});
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// 128 bit load/store is atomic on Armv8.4+
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u128 result = *reinterpret_cast<u128*>(jump_instrs);
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#if defined(__APPLE__)
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pthread_jit_write_protect_np(false);
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#endif
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atomic_storage<u128>::release(*reinterpret_cast<u128*>(rip), result);
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#if defined(__APPLE__)
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pthread_jit_write_protect_np(true);
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#endif
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// Flush all cache lines after potentially writing executable code
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asm("ISB");
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asm("DSB ISH");
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#else
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#error "Unimplemented"
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#endif
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}
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// Second attempt (recover from the recursion after repeated unsuccessful trampoline call)
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@ -1251,13 +1512,27 @@ void spu_recompiler_base::dispatch(spu_thread& spu, void*, u8* rip)
|
|||
spu_log.trace("Called from 0x%x", _info._u32[2] - 4);
|
||||
}
|
||||
}
|
||||
#if defined(__APPLE__)
|
||||
pthread_jit_write_protect_np(true);
|
||||
#endif
|
||||
|
||||
#if defined(ARCH_ARM64)
|
||||
// Flush all cache lines after potentially writing executable code
|
||||
asm("ISB");
|
||||
asm("DSB ISH");
|
||||
#endif
|
||||
spu_runtime::g_tail_escape(&spu, func, nullptr);
|
||||
}
|
||||
|
||||
void spu_recompiler_base::branch(spu_thread& spu, void*, u8* rip)
|
||||
{
|
||||
#if defined(ARCH_X64)
|
||||
if (const u32 ls_off = ((rip[6] << 8) | rip[7]) * 4)
|
||||
#elif defined(ARCH_ARM64)
|
||||
if (const u32 ls_off = ((rip[16] << 8) | rip[17]) * 4) // See branch_patchpoint `data`
|
||||
#else
|
||||
#error "Unimplemented"
|
||||
#endif
|
||||
{
|
||||
spu_log.todo("Special branch patchpoint hit.\nPlease report to the developer (0x%05x).", ls_off);
|
||||
}
|
||||
|
|
@ -1270,6 +1545,7 @@ void spu_recompiler_base::branch(spu_thread& spu, void*, u8* rip)
|
|||
return;
|
||||
}
|
||||
|
||||
#if defined(ARCH_X64)
|
||||
// Overwrite jump to this function with jump to the compiled function
|
||||
const s64 rel = reinterpret_cast<u64>(func) - reinterpret_cast<u64>(rip) - 5;
|
||||
|
||||
|
|
@ -1305,6 +1581,34 @@ void spu_recompiler_base::branch(spu_thread& spu, void*, u8* rip)
|
|||
}
|
||||
|
||||
atomic_storage<u64>::release(*reinterpret_cast<u64*>(rip), result);
|
||||
#elif defined(ARCH_ARM64)
|
||||
auto jmp_instrs = build_function_asm<spu_function_t>("", [&](native_asm& c, auto& args)
|
||||
{
|
||||
using namespace asmjit;
|
||||
|
||||
Label branch_target = c.newLabel();
|
||||
c.ldr(a64::x9, arm::Mem(branch_target)); // PC rel load
|
||||
c.br(a64::x9);
|
||||
|
||||
c.bind(branch_target);
|
||||
c.embedUInt64(reinterpret_cast<u64>(func));
|
||||
});
|
||||
// 128 bit load/store is atomic on Armv8.4+
|
||||
u128 result = *reinterpret_cast<u128*>(jmp_instrs);
|
||||
#if defined(__APPLE__)
|
||||
pthread_jit_write_protect_np(false);
|
||||
#endif
|
||||
atomic_storage<u128>::release(*reinterpret_cast<u128*>(rip), result);
|
||||
#if defined(__APPLE__)
|
||||
pthread_jit_write_protect_np(true);
|
||||
#endif
|
||||
|
||||
// Flush all cache lines after potentially writing executable code
|
||||
asm("ISB");
|
||||
asm("DSB ISH");
|
||||
#else
|
||||
#error "Unimplemented"
|
||||
#endif
|
||||
|
||||
spu_runtime::g_tail_escape(&spu, func, rip);
|
||||
}
|
||||
|
|
@ -4706,7 +5010,7 @@ public:
|
|||
m_test_state->setLinkage(GlobalValue::InternalLinkage);
|
||||
#ifdef ARCH_ARM64
|
||||
// LLVM doesn't support PreserveAll on arm64.
|
||||
m_test_state->setCallingConv(CallingConv::GHC);
|
||||
m_test_state->setCallingConv(CallingConv::PreserveMost);
|
||||
#else
|
||||
m_test_state->setCallingConv(CallingConv::PreserveAll);
|
||||
#endif
|
||||
|
|
@ -5026,6 +5330,10 @@ public:
|
|||
fmt::throw_exception("Compilation failed");
|
||||
}
|
||||
|
||||
#if defined(__APPLE__)
|
||||
pthread_jit_write_protect_np(false);
|
||||
#endif
|
||||
|
||||
if (g_cfg.core.spu_debug)
|
||||
{
|
||||
// Testing only
|
||||
|
|
@ -5058,6 +5366,15 @@ public:
|
|||
fs::file(m_spurt->get_cache_path() + "spu-ir.log", fs::write + fs::append).write(log);
|
||||
}
|
||||
|
||||
#if defined(__APPLE__)
|
||||
pthread_jit_write_protect_np(true);
|
||||
#endif
|
||||
#if defined(ARCH_ARM64)
|
||||
// Flush all cache lines after potentially writing executable code
|
||||
asm("ISB");
|
||||
asm("DSB ISH");
|
||||
#endif
|
||||
|
||||
if (g_fxo->get<spu_cache>().operator bool())
|
||||
{
|
||||
spu_log.success("New block compiled successfully");
|
||||
|
|
|
|||
|
|
@ -260,7 +260,7 @@ namespace utils
|
|||
|
||||
#ifdef __APPLE__
|
||||
#ifdef ARCH_ARM64
|
||||
auto ptr = ::mmap(use_addr, size, PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE | MAP_JIT | c_map_noreserve, -1, 0);
|
||||
auto ptr = ::mmap(use_addr, size, PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE | MAP_JIT | c_map_noreserve, -1, 0);
|
||||
#else
|
||||
auto ptr = ::mmap(use_addr, size, PROT_NONE, MAP_ANON | MAP_PRIVATE | MAP_JIT | c_map_noreserve, -1, 0);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue