From a2da5250644ff1eca454525a8db2147ffb72988d Mon Sep 17 00:00:00 2001 From: Megamouse Date: Sat, 29 May 2021 10:23:28 +0200 Subject: [PATCH] cellVdec: silence "Unsupported time_base" error log spam --- rpcs3/Emu/Cell/Modules/cellVdec.cpp | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/rpcs3/Emu/Cell/Modules/cellVdec.cpp b/rpcs3/Emu/Cell/Modules/cellVdec.cpp index 4821c0d67a..7c3c171b58 100644 --- a/rpcs3/Emu/Cell/Modules/cellVdec.cpp +++ b/rpcs3/Emu/Cell/Modules/cellVdec.cpp @@ -127,6 +127,8 @@ struct vdec_context final lf_queue> in_cmd; + AVRational log_time_base{}; // Used to reduce log spam + vdec_context(s32 type, u32 /*profile*/, u32 addr, u32 size, vm::ptr func, u32 arg) : type(type) , mem_addr(addr) @@ -237,6 +239,8 @@ struct vdec_context final { avcodec_flush_buffers(ctx); + log_time_base = {}; + frc_set = 0; // TODO: ??? next_pts = 0; next_dts = 0; @@ -376,6 +380,12 @@ struct vdec_context final } else if (ctx->time_base.num == 0) { + if (log_time_base.den != ctx->time_base.den || log_time_base.num != ctx->time_base.num) + { + cellVdec.error("time_base.num is 0 (%d/%d, tpf=%d framerate=%d/%d)", ctx->time_base.num, ctx->time_base.den, ctx->ticks_per_frame, ctx->framerate.num, ctx->framerate.den); + log_time_base = ctx->time_base; + } + // Hack const u64 amend = u64{90000} / 30; frame.frc = CELL_VDEC_FRC_30; @@ -405,8 +415,14 @@ struct vdec_context final frame.frc = CELL_VDEC_FRC_60; else { + if (log_time_base.den != ctx->time_base.den || log_time_base.num != ctx->time_base.num) + { + // 1/1000 usually means that the time stamps are written in 1ms units and that the frame rate may vary. + cellVdec.error("Unsupported time_base (%d/%d, tpf=%d framerate=%d/%d)", ctx->time_base.num, ctx->time_base.den, ctx->ticks_per_frame, ctx->framerate.num, ctx->framerate.den); + log_time_base = ctx->time_base; + } + // Hack - cellVdec.error("Unsupported time_base.num (%d/%d, tpf=%d)", ctx->time_base.den, ctx->time_base.num, ctx->ticks_per_frame); amend = u64{90000} / 30; frame.frc = CELL_VDEC_FRC_30; }