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rsx: Fix wrapped/clamped MSAA sampling behavior with dynamic flags

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kd-11 2024-06-27 01:12:53 +03:00 • committed by Megamouse
parent 703de01ebf
commit a5956cfa82
7 changed files with 59 additions and 3 deletions
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22
rpcs3/Emu/RSX/Common/TextureUtils.cpp
View file

@ -1549,4 +1549,26 @@ namespace rsx
{
return get_format_block_size_in_bytes(format) == 2 ? 0xFFFF : 0xFFFFFF;
}
bool is_texcoord_wrapping_mode(rsx::texture_wrap_mode mode)
{
switch (mode)
{
// Clamping modes
default:
rsx_log.error("Unknown texture wrap mode: %d", static_cast<int>(mode));
[[ fallthrough ]];
case rsx::texture_wrap_mode::border:
case rsx::texture_wrap_mode::clamp:
case rsx::texture_wrap_mode::clamp_to_edge:
case rsx::texture_wrap_mode::mirror_once_clamp_to_edge:
case rsx::texture_wrap_mode::mirror_once_border:
case rsx::texture_wrap_mode::mirror_once_clamp:
return false;
// Wrapping modes
case rsx::texture_wrap_mode::wrap:
case rsx::texture_wrap_mode::mirror:
return true;
}
}
}

2
rpcs3/Emu/RSX/Common/TextureUtils.h
View file

@ -286,4 +286,6 @@ namespace rsx
format_class classify_format(rsx::surface_depth_format2 format);
format_class classify_format(u32 gcm_format);
bool is_texcoord_wrapping_mode(rsx::texture_wrap_mode mode);
}

3
rpcs3/Emu/RSX/Program/GLSLCommon.cpp
View file

@ -332,6 +332,9 @@ namespace glsl
{ "SEXT_G_BIT" , rsx::texture_control_bits::SEXT_G },
{ "SEXT_B_BIT" , rsx::texture_control_bits::SEXT_B },
{ "SEXT_A_BIT" , rsx::texture_control_bits::SEXT_A },
{ "WRAP_S_BIT", rsx::texture_control_bits::WRAP_S },
{ "WRAP_T_BIT", rsx::texture_control_bits::WRAP_T },
{ "WRAP_R_BIT", rsx::texture_control_bits::WRAP_R },
{ "ALPHAKILL ", rsx::texture_control_bits::ALPHAKILL },
{ "RENORMALIZE ", rsx::texture_control_bits::RENORMALIZE },

3
rpcs3/Emu/RSX/Program/GLSLCommon.h
View file

@ -34,6 +34,9 @@ namespace rsx
FILTERED_MIN,
UNNORMALIZED_COORDS,
CLAMP_TEXCOORDS_BIT,
WRAP_S,
WRAP_T,
WRAP_R,
GAMMA_CTRL_MASK = (1 << GAMMA_R) | (1 << GAMMA_G) | (1 << GAMMA_B) | (1 << GAMMA_A),
EXPAND_MASK = (1 << EXPAND_R) | (1 << EXPAND_G) | (1 << EXPAND_B) | (1 << EXPAND_A),

14
rpcs3/Emu/RSX/Program/GLSLSnippets/RSXProg/RSXFragmentTextureMSAAOpsInternal.glsl
View file

@ -1,4 +1,16 @@
R"(
vec2 texture2DMSCoord(const in vec2 coords, const in uint flags)
{
if (0u == (flags & (WRAP_S_MASK | WRAP_T_MASK)))
{
return coords;
}
const vec2 wrapped_coords = mod(coords, vec2(1.0));
const bvec2 wrap_control_mask = bvec2(uvec2(flags) & uvec2(WRAP_S_MASK, WRAP_T_MASK));
return _select(coords, wrapped_coords, wrap_control_mask);
}
vec4 texelFetch2DMS(in _MSAA_SAMPLER_TYPE_ tex, const in vec2 sample_count, const in ivec2 icoords, const in int index, const in ivec2 offset)
{
const vec2 resolve_coords = vec2(icoords + offset);
@ -12,7 +24,7 @@ vec4 sampleTexture2DMS(in _MSAA_SAMPLER_TYPE_ tex, const in vec2 coords, const i
{
const uint flags = TEX_FLAGS(index);
const vec2 scaled_coords = COORD_SCALE2(index, coords);
const vec2 normalized_coords = mod(scaled_coords, vec2(1.0));
const vec2 normalized_coords = texture2DMSCoord(scaled_coords, flags);
const vec2 sample_count = vec2(2., textureSamples(tex) * 0.5);
const vec2 image_size = textureSize(tex) * sample_count;
const ivec2 icoords = ivec2(normalized_coords * image_size);

3
rpcs3/Emu/RSX/Program/GLSLSnippets/RSXProg/RSXFragmentTextureOps.glsl
View file

@ -11,6 +11,9 @@ R"(
#define SEXT_G_MASK (1 << SEXT_G_BIT)
#define SEXT_B_MASK (1 << SEXT_B_BIT)
#define SEXT_A_MASK (1 << SEXT_A_BIT)
#define WRAP_S_MASK (1 << WRAP_S_BIT)
#define WRAP_T_MASK (1 << WRAP_T_BIT)
#define WRAP_R_MASK (1 << WRAP_R_BIT)
#define GAMMA_CTRL_MASK (GAMMA_R_MASK | GAMMA_G_MASK | GAMMA_B_MASK | GAMMA_A_MASK)
#define SIGN_EXPAND_MASK (EXPAND_R_MASK | EXPAND_G_MASK | EXPAND_B_MASK | EXPAND_A_MASK)

15
rpcs3/Emu/RSX/RSXThread.cpp
View file

@ -2525,14 +2525,25 @@ namespace rsx
}
}
if (backend_config.supports_hw_msaa &&
sampler_descriptors[i]->samples > 1)
if (backend_config.supports_hw_msaa && sampler_descriptors[i]->samples > 1)
{
current_fp_texture_state.multisampled_textures |= (1 << i);
texture_control |= (static_cast<u32>(tex.zfunc()) << texture_control_bits::DEPTH_COMPARE_OP);
texture_control |= (static_cast<u32>(tex.mag_filter() != rsx::texture_magnify_filter::nearest) << texture_control_bits::FILTERED_MAG);
texture_control |= (static_cast<u32>(tex.min_filter() != rsx::texture_minify_filter::nearest) << texture_control_bits::FILTERED_MIN);
texture_control |= (((tex.format() & CELL_GCM_TEXTURE_UN) >> 6) << texture_control_bits::UNNORMALIZED_COORDS);
if (rsx::is_texcoord_wrapping_mode(tex.wrap_s())) {
texture_control |= (1 << texture_control_bits::WRAP_S);
}
if (rsx::is_texcoord_wrapping_mode(tex.wrap_t())) {
texture_control |= (1 << texture_control_bits::WRAP_T);
}
if (rsx::is_texcoord_wrapping_mode(tex.wrap_r())) {
texture_control |= (1 << texture_control_bits::WRAP_R);
}
}
if (sampler_descriptors[i]->format_class != RSX_FORMAT_CLASS_COLOR)