diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h
index d31a197144..8fe80c47aa 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.h
+++ b/rpcs3/Emu/Cell/PPUDisAsm.h
@@ -1320,6 +1320,10 @@ private:
 	{
 		DisAsm_R3_RC("andc", ra, rs, rb, rc);
 	}
+	void TD(u32 to, u32 ra, u32 rb)
+	{
+		DisAsm_INT1_R2("td", to, ra, rb);
+	}
 	void LVEWX(u32 vd, u32 ra, u32 rb)
 	{
 		DisAsm_V1_R2("lvewx", vd, ra, rb);
diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index 5ce51768a1..a01c16fe3a 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -470,6 +470,7 @@ namespace PPU_instr
 	/*0x037*/bind_instr(g1f_list, LWZUX, RD, RA, RB);
 	/*0x03a*/bind_instr(g1f_list, CNTLZD, RA, RS, RC);
 	/*0x03c*/bind_instr(g1f_list, ANDC, RA, RS, RB, RC);
+	/*0x03c*/bind_instr(g1f_list, TD, TO, RA, RB);
 	/*0x047*/bind_instr(g1f_list, LVEWX, VD, RA, RB);
 	/*0x049*/bind_instr(g1f_list, MULHD, RD, RA, RB, RC);
 	/*0x04b*/bind_instr(g1f_list, MULHW, RD, RA, RB, RC);
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h
index ea9d73444a..209cdafd14 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter.h
@@ -2518,6 +2518,10 @@ private:
 		CPU.GPR[ra] = CPU.GPR[rs] & ~CPU.GPR[rb];
 		if(rc) CPU.UpdateCR0<s64>(CPU.GPR[ra]);
 	}
+	void TD(u32 to, u32 ra, u32 rb)
+	{
+		UNK("td");
+	}
 	void LVEWX(u32 vd, u32 ra, u32 rb)
 	{
 		//const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL;
diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h
index 008a07c879..223f7a9eef 100644
--- a/rpcs3/Emu/Cell/PPUOpcodes.h
+++ b/rpcs3/Emu/Cell/PPUOpcodes.h
@@ -280,6 +280,7 @@ namespace PPU_opcodes
 		LWZUX  = 0x037,
 		CNTLZD = 0x03a,
 		ANDC   = 0x03c,
+		TD     = 0x044,
 		LVEWX  = 0x047, //Load Vector Element Word Indexed
 		MULHD  = 0x049,
 		MULHW  = 0x04b,
@@ -676,6 +677,7 @@ public:
 	virtual void LWZUX(u32 rd, u32 ra, u32 rb) = 0;
 	virtual void CNTLZD(u32 ra, u32 rs, bool rc) = 0;
 	virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) = 0;
+	virtual void TD(u32 to, u32 ra, u32 rb) = 0;
 	virtual void LVEWX(u32 vd, u32 ra, u32 rb) = 0;
 	virtual void MULHD(u32 rd, u32 ra, u32 rb, bool rc) = 0;
 	virtual void MULHW(u32 rd, u32 ra, u32 rb, bool rc) = 0;