diff --git a/rpcs3/Emu/Cell/lv2/sys_rwlock.cpp b/rpcs3/Emu/Cell/lv2/sys_rwlock.cpp
index 31ffbc98d9..4aaf4e1655 100644
--- a/rpcs3/Emu/Cell/lv2/sys_rwlock.cpp
+++ b/rpcs3/Emu/Cell/lv2/sys_rwlock.cpp
@@ -169,17 +169,18 @@ error_code sys_rwlock_tryrlock(u32 rw_lock_id)
 
 	const auto rwlock = idm::check<lv2_obj, lv2_rwlock>(rw_lock_id, [](lv2_rwlock& rwlock)
 	{
-		const s64 val = rwlock.owner;
-
-		if (val <= 0 && !(val & 1))
+		auto [_, ok] = rwlock.owner.fetch_op([](s64& val)
 		{
-			if (rwlock.owner.compare_and_swap_test(val, val - 2))
+			if (val <= 0 && !(val & 1))
 			{
+				val -= 2;
 				return true;
 			}
-		}
 
-		return false;
+			return false;
+		});
+
+		return ok;
 	});
 
 	if (!rwlock)
diff --git a/rpcs3/Emu/Cell/lv2/sys_semaphore.cpp b/rpcs3/Emu/Cell/lv2/sys_semaphore.cpp
index 18c07ca7b2..c82f633d4d 100644
--- a/rpcs3/Emu/Cell/lv2/sys_semaphore.cpp
+++ b/rpcs3/Emu/Cell/lv2/sys_semaphore.cpp
@@ -171,17 +171,7 @@ error_code sys_semaphore_trywait(u32 sem_id)
 
 	const auto sem = idm::check<lv2_obj, lv2_sema>(sem_id, [&](lv2_sema& sema)
 	{
-		const s32 val = sema.val;
-
-		if (val > 0)
-		{
-			if (sema.val.compare_and_swap_test(val, val - 1))
-			{
-				return true;
-			}
-		}
-
-		return false;
+		return sema.val.try_dec(0);
 	});
 
 	if (!sem)