mirrors/rpcs3
1
0
Fork 0
mirror of https://github.com/RPCS3/rpcs3.git synced 2025-04-20 03:25:16 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

SPU branch D/E flags workaround

Browse source
This commit is contained in:
Nekotekina 2014-10-10 01:38:02 +04:00
parent 1dac13be16
commit b7d0bfa972
3 changed files with 62 additions and 38 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

48
rpcs3/Emu/Cell/SPUInterpreter.h
View file

@ -251,10 +251,12 @@ private:
}
void BIZ(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@ -270,10 +272,12 @@ private:
}
void BINZ(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@ -289,10 +293,12 @@ private:
}
void BIHZ(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@ -308,10 +314,12 @@ private:
}
void BIHNZ(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@ -337,10 +345,12 @@ private:
}
void BI(u32 intr, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@ -349,10 +359,12 @@ private:
}
void BISL(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);

48
rpcs3/Emu/Cell/SPURecompiler.h
View file

@ -1074,10 +1074,12 @@ private:
}
void BIZ(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
c.mov(cpu_dword(PC), CPU.PC);
@ -1093,10 +1095,12 @@ private:
}
void BINZ(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
c.mov(cpu_dword(PC), CPU.PC);
@ -1112,10 +1116,12 @@ private:
}
void BIHZ(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
c.mov(cpu_dword(PC), CPU.PC);
@ -1131,10 +1137,12 @@ private:
}
void BIHNZ(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
c.mov(cpu_dword(PC), CPU.PC);
@ -1181,10 +1189,12 @@ private:
}
void BI(u32 intr, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
c.mov(cpu_dword(PC), CPU.PC);
@ -1197,10 +1207,12 @@ private:
}
void BISL(u32 intr, u32 rt, u32 ra)
{
if (intr)
switch (intr)
{
UNIMPLEMENTED();
return;
case 0: break;
case 0x10: break; // enable interrupts
case 0x20: break; // disable interrupts
default: UNIMPLEMENTED(); return;
}
XmmInvalidate(rt);

4
rpcs3/Emu/SysCalls/Modules/cellGcmSys.cpp
View file

@ -933,8 +933,8 @@ s32 cellGcmMapMainMemory(u32 ea, u32 size, vm::ptr<be_t<u32>> offset)
//fill the offset table
for (u32 i = 0; i<(size >> 20); i++)
{
offsetTable.ioAddress[(ea >> 20) + i] = (u16)(io >> 20) + i;
offsetTable.eaAddress[(io >> 20) + i] = (u16)(ea >> 20) + i;
offsetTable.ioAddress[(ea >> 20) + i] = (u16)((io >> 20) + i);
offsetTable.eaAddress[(io >> 20) + i] = (u16)((ea >> 20) + i);
Emu.GetGSManager().GetRender().m_strict_ordering[(io >> 20) + i] = false;
}