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simd.hpp: add some intrinsics
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capriots
parent
f9cc83c285
commit
c3691b1742
1 changed files with 131 additions and 7 deletions
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@ -21,6 +21,7 @@
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#include <arm_neon.h>
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#endif
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#include <algorithm>
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#include <cmath>
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#include <math.h>
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#include <cfenv>
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@ -1967,6 +1968,15 @@ inline v128 gv_mulfs(const v128& a, const v128& b)
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#endif
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}
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inline v128 gv_mulfs(const v128& a, f32 b)
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{
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#if defined(ARCH_X64)
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return _mm_mul_ps(a, _mm_set_ps1(b));
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#elif defined(ARCH_ARM64)
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return vmulq_n_f32(a, b);
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#endif
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}
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inline v128 gv_hadds8x2(const v128& a)
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{
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#if defined(__SSSE3__)
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@ -2979,6 +2989,23 @@ inline v128 gv_rol16(const v128& a, const v128& b)
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#endif
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}
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// For each 16-bit element, r = rotate a by count
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template <u8 Count>
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inline v128 gv_rol16(const v128& a)
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{
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constexpr u8 count = Count & 0xf;
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#if defined(ARCH_X64)
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return _mm_or_si128(_mm_srli_epi16(a, 16 - count), _mm_slli_epi16(a, count));
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#elif defined(ARCH_ARM64)
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return vorrq_u16(vshrq_n_u16(a, 16 - count), vshlq_n_u16(a, count));
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#else
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v128 r;
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for (u32 i = 0; i < 8; i++)
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r._u16[i] = std::rotl(a._u16[i], count);
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return r;
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#endif
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}
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// For each 32-bit element, r = rotate a by b
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inline v128 gv_rol32(const v128& a, const v128& b)
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{
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@ -2997,15 +3024,16 @@ inline v128 gv_rol32(const v128& a, const v128& b)
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}
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// For each 32-bit element, r = rotate a by count
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inline v128 gv_rol32(const v128& a, u32 count)
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template <u8 Count>
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inline v128 gv_rol32(const v128& a)
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{
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count %= 32;
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#if defined(ARCH_X64)
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return _mm_or_epi32(_mm_srli_epi32(a, 32 - count), _mm_slli_epi32(a, count));
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constexpr u8 count = Count & 0x1f;
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#if defined(__AVX512VL__)
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return _mm_rol_epi32(a, count);
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#elif defined(ARCH_X64)
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return _mm_or_si128(_mm_srli_epi32(a, 32 - count), _mm_slli_epi32(a, count));
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#elif defined(ARCH_ARM64)
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const auto amt1 = vdupq_n_s32(count);
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const auto amt2 = vdupq_n_s32(count - 32);
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return vorrq_u32(vshlq_u32(a, amt1), vshlq_u32(a, amt2));
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return vorrq_u32(vshrq_n_u32(a, 32 - count), vshlq_n_u32(a, count));
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#else
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v128 r;
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for (u32 i = 0; i < 4; i++)
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@ -3107,6 +3135,102 @@ inline auto gv_shuffle_right(A&& a)
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FOR_X64(unary_op, kIdPsrldq, kIdVpsrldq, std::forward<A>(a), Count);
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}
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// Load 32-bit integer into the first element of a new vector, set other elements to zero
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inline v128 gv_loadu32(const void* ptr)
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{
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#if defined(ARCH_X64)
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return _mm_loadu_si32(ptr);
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#elif defined(ARCH_ARM64)
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return vld1q_lane_u32(static_cast<const u32*>(ptr), vdupq_n_u32(0), 0);
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#endif
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}
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// Load 16-bit integer into an existing vector at the position specified by Index
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template <u8 Index>
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inline v128 gv_insert16(const v128& vec, u16 value)
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{
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#if defined(ARCH_X64)
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return _mm_insert_epi16(vec, value, Index);
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#elif defined(ARCH_ARM64)
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return vsetq_lane_u16(value, vec, Index & 0x7);
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#endif
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}
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// For each 8-bit element,
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// if ctrl >= 0 && ctrl < 16 then r = vec[ctrl],
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// else if ctrl < 0 then r = 0
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inline v128 gv_shuffle8(const v128& vec, const v128& ctrl)
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{
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AUDIT(std::ranges::none_of(ctrl._chars, [](s8 i){ return i >= static_cast<s8>(sizeof(v128)); }), "All indices must be in the range [0, 15] or negative, since PSHUFB and TBL behave differently otherwise");
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#if defined(__SSSE3__)
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return _mm_shuffle_epi8(vec, ctrl);
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#elif defined(ARCH_ARM64)
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return vqtbl1q_s8(vec, ctrl);
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#else
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v128 r;
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for (s32 i = 0; i < 16; i++)
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r._s8[i] = ctrl._s8[i] < 0 ? 0 : vec._s8[ctrl._s8[i] & 0xf];
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return r;
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#endif
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}
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// For each 2-bit index in Control, r = vec[index]
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template <u8 Control>
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inline v128 gv_shuffle32(const v128& vec)
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{
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#if defined(ARCH_X64)
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return _mm_shuffle_epi32(vec, Control);
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#elif defined(ARCH_ARM64)
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constexpr u8 idx0 = (Control & 3) * sizeof(s32);
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constexpr u8 idx1 = (Control >> 2 & 3) * sizeof(s32);
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constexpr u8 idx2 = (Control >> 4 & 3) * sizeof(s32);
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constexpr u8 idx3 = (Control >> 6 & 3) * sizeof(s32);
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constexpr uint8x16_t idx_vec = { idx0, idx0 + 1, idx0 + 2, idx0 + 3, idx1, idx1 + 1, idx1 + 2, idx1 + 3, idx2, idx2 + 1, idx2 + 2, idx2 + 3, idx3, idx3 + 1, idx3 + 2, idx3 + 3 };
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return vqtbl1q_s8(vec, idx_vec);
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#endif
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}
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// For the first two 2-bit indices in Control, r = a[index],
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// for the last two indices, r = b[index]
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template <u8 Control>
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inline v128 gv_shufflefs(const v128& a, const v128& b)
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{
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#if defined(ARCH_X64)
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return _mm_shuffle_ps(a, b, Control);
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#elif defined(ARCH_ARM64)
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constexpr u8 idx0 = (Control & 3) * sizeof(s32);
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constexpr u8 idx1 = (Control >> 2 & 3) * sizeof(s32);
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constexpr u8 idx2 = (Control >> 4 & 3) * sizeof(s32) + sizeof(v128);
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constexpr u8 idx3 = (Control >> 6 & 3) * sizeof(s32) + sizeof(v128);
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constexpr uint8x16_t idx_vec = { idx0, idx0 + 1, idx0 + 2, idx0 + 3, idx1, idx1 + 1, idx1 + 2, idx1 + 3, idx2, idx2 + 1, idx2 + 2, idx2 + 3, idx3, idx3 + 1, idx3 + 2, idx3 + 3 };
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return vqtbl2q_s8({ a, b }, idx_vec);
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#endif
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}
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// For each 32-bit element, reverse byte order
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inline v128 gv_rev32(const v128& vec)
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{
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#if defined(__SSSE3__)
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return _mm_shuffle_epi8(vec, _mm_setr_epi8(3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12));
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#elif defined(ARCH_ARM64)
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return vrev32q_u8(vec);
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#else
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return gv_rol32<16>(gv_rol16<8>(vec));
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#endif
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}
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// For each 32-bit element, convert between big-endian and native-endian
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inline v128 gv_to_be32(const v128& vec)
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{
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if constexpr (std::endian::native == std::endian::little)
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return gv_rev32(vec);
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return vec;
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}
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#if defined(__clang__)
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#pragma clang diagnostic pop
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#elif defined(__GNUC__)
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