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vk: Short-circuit program load if state did not change
- TODO: Incorporate VK_EXT_extended_dynamic_state
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3dd6e5664c
commit
c7fed20f3c
3 changed files with 36 additions and 3 deletions
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@ -1743,6 +1743,8 @@ void VKGSRender::do_local_task(rsx::FIFO::state state)
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bool VKGSRender::load_program()
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{
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const auto shadermode = g_cfg.video.shadermode.get();
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if (m_graphics_state & rsx::pipeline_state::invalidate_pipeline_bits)
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{
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get_current_fragment_program(fs_sampler_state);
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@ -1752,10 +1754,25 @@ bool VKGSRender::load_program()
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m_graphics_state &= ~rsx::pipeline_state::invalidate_pipeline_bits;
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}
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else if (!(m_graphics_state & rsx::pipeline_state::pipeline_config_dirty) && m_program)
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{
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if (!m_shader_interpreter.is_interpreter(m_program)) [[ likely ]]
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{
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return true;
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}
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if (shadermode == shader_mode::interpreter_only)
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{
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m_program = m_shader_interpreter.get(m_pipeline_properties, current_fp_metadata);
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return true;
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}
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}
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auto &vertex_program = current_vertex_program;
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auto &fragment_program = current_fragment_program;
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m_cached_draw_state.prim = rsx::method_registers.current_draw_clause.primitive;
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vk::pipeline_props properties{};
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// Input assembly
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@ -1915,7 +1932,6 @@ bool VKGSRender::load_program()
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}
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}
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const auto shadermode = g_cfg.video.shadermode.get();
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m_vertex_prog = nullptr;
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m_fragment_prog = nullptr;
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@ -1966,6 +1982,7 @@ bool VKGSRender::load_program()
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}
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m_pipeline_properties = properties;
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m_graphics_state &= ~rsx::pipeline_state::pipeline_config_dirty;
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return m_program != nullptr;
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}
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@ -94,7 +94,6 @@ private:
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struct
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{
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rsx::primitive_type prim = rsx::primitive_type::points;
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bool primitive_restart = false;
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} m_cached_draw_state;
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public:
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@ -820,6 +820,7 @@ namespace rsx
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if (arg != method_registers.register_previous_value)
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{
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rsx->on_framebuffer_options_changed(reg);
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rsx->m_graphics_state |= rsx::pipeline_config_dirty;
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}
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}
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@ -2531,6 +2532,23 @@ namespace rsx
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state_signals[NV4097_SET_DEPTH_BOUNDS_MAX] = rsx::depth_bounds_state_dirty;
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state_signals[NV4097_SET_FRONT_FACE] = rsx::pipeline_config_dirty;
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state_signals[NV4097_SET_ZMIN_MAX_CONTROL] = rsx::pipeline_config_dirty;
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state_signals[NV4097_SET_LOGIC_OP_ENABLE] = rsx::pipeline_config_dirty;
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state_signals[NV4097_SET_LOGIC_OP] = rsx::pipeline_config_dirty;
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state_signals[NV4097_SET_BLEND_ENABLE] = rsx::pipeline_config_dirty;
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state_signals[NV4097_SET_BLEND_ENABLE_MRT] = rsx::pipeline_config_dirty;
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state_signals[NV4097_SET_STENCIL_FUNC] = rsx::pipeline_config_dirty;
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state_signals[NV4097_SET_BACK_STENCIL_FUNC] = rsx::pipeline_config_dirty;
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state_signals[NV4097_SET_ANTI_ALIASING_CONTROL] = rsx::pipeline_config_dirty;
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state_signals[NV4097_SET_RESTART_INDEX_ENABLE] = rsx::pipeline_config_dirty;
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}
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// Sanity checks
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for (size_t id = 0; id < methods.size(); ++id)
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{
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if (methods[id] && state_signals[id])
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{
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rsx_log.error("FIXME: Method register 0x%x is registered as a method and signal. The signal will be ignored.");
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}
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}
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}
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@ -3534,7 +3552,6 @@ namespace rsx
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bind(NV4097_CLEAR_ZCULL_SURFACE, nv4097::clear_zcull);
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bind(NV4097_SET_DEPTH_TEST_ENABLE, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_DEPTH_FUNC, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_STENCIL_TEST_ENABLE, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_DEPTH_MASK, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_COLOR_MASK, nv4097::set_surface_options_dirty_bit);
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bind(NV4097_SET_COLOR_MASK_MRT, nv4097::set_surface_options_dirty_bit);
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