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https://github.com/RPCS3/rpcs3.git
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PPU LLVM: v2, simplification (no allocas)
This commit is contained in:
Nekotekina
parent
45fae363c6
commit
cd4f290d3d
4 changed files with 142 additions and 166 deletions
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@ -1205,7 +1205,7 @@ extern void ppu_initialize(const ppu_module& info)
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sha1_finish(&ctx, output);
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// Version, module name and hash: vX-liblv2.sprx-0123456789ABCDEF.obj
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fmt::append(obj_name, "v1%s-%016X-%s.obj", part.name, reinterpret_cast<be_t<u64>&>(output), jit.cpu());
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fmt::append(obj_name, "v2%s-%016X-%s.obj", part.name, reinterpret_cast<be_t<u64>&>(output), jit.cpu());
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}
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if (Emu.IsStopped())
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@ -1352,7 +1352,7 @@ static void ppu_initialize2(jit_compiler& jit, const ppu_module& module_part, co
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Emu.CallAfter([=]()
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{
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dlg->Create("Compiling PPU module " + obj_name + "\nPlease wait...");
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dlg->Create("Compiling PPU module:\n" + obj_name + "\nPlease wait...");
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});
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// Translate functions
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@ -38,11 +38,23 @@ public:
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f64 fpr[32] = {}; // Floating Point Registers
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v128 vr[32] = {}; // Vector Registers
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alignas(16) bool cr[32] = {}; // Condition Registers (abstract representation)
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alignas(16) bool cr[32] = {}; // Condition Registers (unpacked)
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alignas(16) struct // Floating-Point Status and Control Register (unpacked)
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{
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// TODO
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bool _start[16]{};
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bool fl{}; // FPCC.FL
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bool fg{}; // FPCC.FG
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bool fe{}; // FPCC.FE
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bool fu{}; // FPCC.FU
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bool _end[12]{};
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}
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fpscr;
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u64 lr{}; // Link Register
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u64 ctr{}; // Counter Register
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u32 vrsave{0xffffffff}; // VR Save Register (almost unused)
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u32 vrsave{0xffffffff}; // VR Save Register
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u32 cia{}; // Current Instruction Address
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// Pack CR bits
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@ -111,15 +123,6 @@ public:
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*/
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bool nj = true;
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struct // Floating-Point Status and Control Register (abstract representation)
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{
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bool fl{}; // FPCC.FL
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bool fg{}; // FPCC.FG
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bool fe{}; // FPCC.FE
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bool fu{}; // FPCC.FU
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}
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fpscr;
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u32 raddr{0}; // Reservation addr
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u64 rtime{0};
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u64 rdata{0}; // Reservation data
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@ -85,11 +85,12 @@ PPUTranslator::PPUTranslator(LLVMContext& context, Module* module, u64 base)
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thread_struct.insert(thread_struct.end(), 32, GetType<f64>()); // fpr[0..31]
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thread_struct.insert(thread_struct.end(), 32, GetType<u32[4]>()); // vr[0..31]
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thread_struct.insert(thread_struct.end(), 32, GetType<bool>()); // cr[0..31]
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thread_struct.insert(thread_struct.end(), 32, GetType<bool>()); // fpscr
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thread_struct.insert(thread_struct.end(), 2, GetType<u64>()); // lr, ctr
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thread_struct.insert(thread_struct.end(), 2, GetType<u32>()); // vrsave, cia
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thread_struct.insert(thread_struct.end(), 3, GetType<bool>()); // so, ov, ca
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thread_struct.insert(thread_struct.end(), 1, GetType<u8>()); // cnt
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thread_struct.insert(thread_struct.end(), 6, GetType<bool>()); // sat, nj, FPCC
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thread_struct.insert(thread_struct.end(), 2, GetType<bool>()); // sat, nj
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m_thread_type = StructType::create(m_context, thread_struct, "context_t");
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@ -122,19 +123,24 @@ Function* PPUTranslator::Translate(const ppu_function& info)
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std::fill(std::begin(m_globals), std::end(m_globals), nullptr);
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std::fill(std::begin(m_locals), std::end(m_locals), nullptr);
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std::fill(std::begin(m_writes), std::end(m_writes), false);
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std::fill(std::begin(m_reads), std::end(m_reads), false);
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/* Create builders */
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IRBuilder<> irb(m_entry = BasicBlock::Create(m_context, "__entry", m_function));
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m_ir = &irb;
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m_body = BasicBlock::Create(m_context, "__body", m_function);
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irb.SetInsertPoint(m_body);
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/* Create context variables */
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m_thread = &*m_function->getArgumentList().begin();
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m_base_loaded = m_ir->CreateLoad(m_base);
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m_body = BasicBlock::Create(m_context, "__body", m_function);
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// Check status register in the entry block
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const auto vstate = m_ir->CreateLoad(m_ir->CreateStructGEP(nullptr, m_thread, 1), true);
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const auto vcheck = BasicBlock::Create(m_context, "__test", m_function);
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m_ir->CreateCondBr(m_ir->CreateIsNull(vstate), m_body, vcheck, m_md_likely);
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// Create tail call to the check function
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m_ir->SetInsertPoint(vcheck);
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Call(GetType<void>(), "__check", m_thread, m_ir->getInt64(m_start_addr));
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m_ir->CreateRetVoid();
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m_ir->SetInsertPoint(m_body);
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// Process blocks
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const auto block = std::make_pair(info.addr, info.size);
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@ -211,61 +217,54 @@ void PPUTranslator::CallFunction(u64 target, Value* indirect)
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m_ir->CreateRetVoid();
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}
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void PPUTranslator::FlushRegisters()
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Value* PPUTranslator::RegInit(Value*& local)
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{
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if (m_entry->getTerminator())
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const auto index = ::narrow<uint>(&local - m_locals);
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if (!m_globals[index])
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{
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return;
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// Initialize global, will be written in FlushRegisters
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m_globals[index] = m_ir->CreateStructGEP(nullptr, m_thread, index);
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}
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auto process = [&](Value*& local, u32 index)
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return m_globals[index];
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}
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Value* PPUTranslator::RegLoad(Value*& local)
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{
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const uint index = ::narrow<uint>(&local - m_locals);
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if (local)
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{
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// Create pointer to the global variable
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m_ir->SetInsertPoint(m_entry);
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const auto ptr = m_ir->CreateStructGEP(nullptr, m_thread, index);
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// Simple load
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assert(!m_globals[index] || m_globals[index]->getType() == local->getType()->getPointerTo());
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return local;
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}
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// Load variable if necessary
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if (m_reads[&local - m_locals])
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// Load from the global value
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local = m_ir->CreateLoad(m_ir->CreateStructGEP(nullptr, m_thread, index));
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return local;
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}
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void PPUTranslator::RegStore(llvm::Value* value, llvm::Value*& local)
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{
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const auto glb = RegInit(local);
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assert(glb->getType() == value->getType()->getPointerTo());
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local = value;
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}
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void PPUTranslator::FlushRegisters()
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{
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for (auto& local : m_locals)
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{
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const uint index = ::narrow<uint>(&local - m_locals);
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if (local && m_globals[index])
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{
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m_ir->CreateStore(m_ir->CreateLoad(ptr), local);
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// Store value if necessary
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m_ir->CreateStore(local, m_globals[index]);
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}
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m_ir->SetInsertPoint(m_body);
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// Store variable if necessary
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if (m_writes[&local - m_locals])
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{
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m_ir->CreateStore(m_ir->CreateLoad(local), ptr);
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}
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// Save global
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m_globals[&local - m_locals] = ptr;
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};
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for (u32 i = 0; i < 32; i++) if (m_gpr[i]) process(m_gpr[i], 3 + i);
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for (u32 i = 0; i < 32; i++) if (m_fpr[i]) process(m_fpr[i], 35 + i);
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for (u32 i = 0; i < 32; i++) if (m_vr[i]) process(m_vr[i], 67 + i);
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for (u32 i = 0; i < 32; i++) if (m_cr[i]) process(m_cr[i], 99 + i);
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if (m_lr) process(m_lr, 131);
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if (m_ctr) process(m_ctr, 132);
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if (m_vrsave) process(m_vrsave, 133);
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if (m_so) process(m_so, 135);
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if (m_ov) process(m_ov, 136);
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if (m_ca) process(m_ca, 137);
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if (m_cnt) process(m_cnt, 138);
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if (m_sat) process(m_sat, 139);
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if (m_nj) process(m_nj, 140);
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for (u32 i = 16; i < 20; i++) if (m_fc[i]) process(m_fc[i], 141 + i - 16);
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m_ir->SetInsertPoint(m_entry);
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const auto vstate = m_ir->CreateLoad(m_ir->CreateStructGEP(nullptr, m_thread, 1), true);
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const auto vcheck = BasicBlock::Create(m_context, "__test", m_function);
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m_ir->CreateCondBr(m_ir->CreateIsNull(vstate), m_body, vcheck, m_md_likely);
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m_ir->SetInsertPoint(vcheck);
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Call(GetType<void>(), "__check", m_thread, m_ir->getInt64(m_start_addr));
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m_ir->CreateRetVoid();
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m_ir->SetInsertPoint(m_body);
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}
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}
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Value* PPUTranslator::Solid(Value* value)
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@ -482,15 +481,15 @@ void PPUTranslator::CompilationError(const std::string& error)
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void PPUTranslator::MFVSCR(ppu_opcode_t op)
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{
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const auto vscr = m_ir->CreateOr(ZExt(RegLoad<bool>(m_sat), GetType<u32>()), m_ir->CreateShl(ZExt(RegLoad<bool>(m_nj), GetType<u32>()), 16));
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const auto vscr = m_ir->CreateOr(ZExt(RegLoad(m_sat), GetType<u32>()), m_ir->CreateShl(ZExt(RegLoad(m_nj), GetType<u32>()), 16));
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SetVr(op.vd, m_ir->CreateInsertElement(ConstantVector::getSplat(4, m_ir->getInt32(0)), vscr, m_ir->getInt32(m_is_be ? 3 : 0)));
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}
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void PPUTranslator::MTVSCR(ppu_opcode_t op)
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{
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const auto vscr = m_ir->CreateExtractElement(GetVr(op.vb, VrType::vi32), m_ir->getInt32(m_is_be ? 3 : 0));
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RegStore<bool>(Trunc(m_ir->CreateLShr(vscr, 16), GetType<bool>()), m_nj);
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RegStore<bool>(Trunc(vscr, GetType<bool>()), m_sat);
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RegStore(Trunc(m_ir->CreateLShr(vscr, 16), GetType<bool>()), m_nj);
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RegStore(Trunc(vscr, GetType<bool>()), m_sat);
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}
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void PPUTranslator::VADDCUW(ppu_opcode_t op)
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@ -1612,7 +1611,7 @@ void PPUTranslator::BC(ppu_opcode_t op)
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{
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if (op.lk)
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{
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RegInit<u64>(m_lr);
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RegInit(m_lr);
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}
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const u64 target = (op.aa ? 0 : m_current_addr) + op.bt14;
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@ -1635,8 +1634,8 @@ void PPUTranslator::SC(ppu_opcode_t op)
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}
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const auto num = GetGpr(11);
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RegStore(m_ir->getInt32(m_current_addr), m_cia);
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FlushRegisters();
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m_ir->CreateStore(m_ir->getInt32(m_current_addr), m_ir->CreateStructGEP(nullptr, m_thread, 134));
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Call(GetType<void>(), op.lev ? "__lv1call" : "__syscall", m_thread, num);
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m_ir->CreateRetVoid();
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}
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@ -1647,7 +1646,7 @@ void PPUTranslator::B(ppu_opcode_t op)
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if (op.lk)
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{
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RegStore<u64>(m_ir->getInt64(m_current_addr + 4), m_lr);
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RegStore(m_ir->getInt64(m_current_addr + 4), m_lr);
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}
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FlushRegisters();
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@ -1665,7 +1664,9 @@ void PPUTranslator::MCRF(ppu_opcode_t op)
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void PPUTranslator::BCLR(ppu_opcode_t op)
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{
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const auto target = RegLoad<u64>(m_lr);
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RegInit(m_lr);
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const auto target = RegLoad(m_lr);
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UseCondition(CheckBranchProbability(op.bo), CheckBranchCondition(op.bo, op.bi));
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@ -1730,10 +1731,10 @@ void PPUTranslator::BCCTR(ppu_opcode_t op)
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{
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if (op.lk)
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{
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RegInit<u64>(m_lr);
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RegInit(m_lr);
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}
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const auto target = RegLoad<u64>(m_ctr);
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const auto target = RegLoad(m_ctr);
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UseCondition(CheckBranchProbability(op.bo | 0x4), CheckBranchCondition(op.bo | 0x4, op.bi));
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@ -2589,19 +2590,19 @@ void PPUTranslator::MFSPR(ppu_opcode_t op)
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switch (const u32 n = (op.spr >> 5) | ((op.spr & 0x1f) << 5))
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{
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case 0x001: // MFXER
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result = ZExt(RegLoad<u8>(m_cnt), GetType<u64>());
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result = m_ir->CreateOr(result, m_ir->CreateShl(ZExt(RegLoad<bool>(m_so), GetType<u64>()), 29));
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result = m_ir->CreateOr(result, m_ir->CreateShl(ZExt(RegLoad<bool>(m_ov), GetType<u64>()), 30));
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result = m_ir->CreateOr(result, m_ir->CreateShl(ZExt(RegLoad<bool>(m_ca), GetType<u64>()), 31));
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result = ZExt(RegLoad(m_cnt), GetType<u64>());
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result = m_ir->CreateOr(result, m_ir->CreateShl(ZExt(RegLoad(m_so), GetType<u64>()), 29));
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result = m_ir->CreateOr(result, m_ir->CreateShl(ZExt(RegLoad(m_ov), GetType<u64>()), 30));
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result = m_ir->CreateOr(result, m_ir->CreateShl(ZExt(RegLoad(m_ca), GetType<u64>()), 31));
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break;
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case 0x008: // MFLR
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result = RegLoad<u64>(m_lr);
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result = RegLoad(m_lr);
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break;
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case 0x009: // MFCTR
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result = RegLoad<u64>(m_ctr);
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result = RegLoad(m_ctr);
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break;
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case 0x100:
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result = ZExt(RegLoad<u32>(m_vrsave));
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result = ZExt(RegLoad(m_vrsave));
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break;
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case 0x10C: // MFTB
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result = Call(GetType<u64>(), m_pure_attr, "__get_tb");
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@ -2733,19 +2734,19 @@ void PPUTranslator::MTSPR(ppu_opcode_t op)
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switch (const u32 n = (op.spr >> 5) | ((op.spr & 0x1f) << 5))
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{
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case 0x001: // MTXER
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RegStore<bool>(Trunc(m_ir->CreateLShr(value, 31), GetType<bool>()), m_ca);
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RegStore<bool>(Trunc(m_ir->CreateLShr(value, 30), GetType<bool>()), m_ov);
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RegStore<bool>(Trunc(m_ir->CreateLShr(value, 29), GetType<bool>()), m_so);
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RegStore<u8>(Trunc(value, GetType<u8>()), m_cnt);
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RegStore(Trunc(m_ir->CreateLShr(value, 31), GetType<bool>()), m_ca);
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RegStore(Trunc(m_ir->CreateLShr(value, 30), GetType<bool>()), m_ov);
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RegStore(Trunc(m_ir->CreateLShr(value, 29), GetType<bool>()), m_so);
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RegStore(Trunc(value, GetType<u8>()), m_cnt);
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break;
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case 0x008: // MTLR
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RegStore<u64>(value, m_lr);
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RegStore(value, m_lr);
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break;
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case 0x009: // MTCTR
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RegStore<u64>(value, m_ctr);
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RegStore(value, m_ctr);
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break;
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case 0x100:
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RegStore<u32>(Trunc(value), m_vrsave);
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RegStore(Trunc(value), m_vrsave);
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break;
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default:
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Call(GetType<void>(), fmt::format("__mtspr_%u", n), value);
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@ -2799,7 +2800,7 @@ void PPUTranslator::LDBRX(ppu_opcode_t op)
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void PPUTranslator::LSWX(ppu_opcode_t op)
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{
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Call(GetType<void>(), "__lswx", m_ir->getInt32(op.rd), RegLoad<u8>(m_cnt), op.ra ? m_ir->CreateAdd(GetGpr(op.ra), GetGpr(op.rb)) : GetGpr(op.rb));
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Call(GetType<void>(), "__lswx", m_ir->getInt32(op.rd), RegLoad(m_cnt), op.ra ? m_ir->CreateAdd(GetGpr(op.ra), GetGpr(op.rb)) : GetGpr(op.rb));
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}
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void PPUTranslator::LWBRX(ppu_opcode_t op)
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@ -2912,7 +2913,7 @@ void PPUTranslator::STDBRX(ppu_opcode_t op)
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void PPUTranslator::STSWX(ppu_opcode_t op)
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{
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Call(GetType<void>(), "__stswx", m_ir->getInt32(op.rs), RegLoad<u8>(m_cnt), op.ra ? m_ir->CreateAdd(GetGpr(op.ra), GetGpr(op.rb)) : GetGpr(op.rb));
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Call(GetType<void>(), "__stswx", m_ir->getInt32(op.rs), RegLoad(m_cnt), op.ra ? m_ir->CreateAdd(GetGpr(op.ra), GetGpr(op.rb)) : GetGpr(op.rb));
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}
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void PPUTranslator::STWBRX(ppu_opcode_t op)
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@ -3503,7 +3504,7 @@ void PPUTranslator::MFFS(ppu_opcode_t op)
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for (u32 i = 16; i < 20; i++)
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{
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result = m_ir->CreateOr(result, m_ir->CreateShl(ZExt(RegLoad<bool>(m_fc[i]), GetType<u64>()), i ^ 31));
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result = m_ir->CreateOr(result, m_ir->CreateShl(ZExt(RegLoad(m_fc[i]), GetType<u64>()), i ^ 31));
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}
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SetFpr(op.frd, result);
|
||||
|
|
@ -3845,17 +3846,17 @@ void PPUTranslator::UNK(ppu_opcode_t op)
|
|||
|
||||
Value* PPUTranslator::GetGpr(u32 r, u32 num_bits)
|
||||
{
|
||||
return m_ir->CreateTrunc(RegLoad<u64>(m_gpr[r]), m_ir->getIntNTy(num_bits));
|
||||
return m_ir->CreateTrunc(RegLoad(m_gpr[r]), m_ir->getIntNTy(num_bits));
|
||||
}
|
||||
|
||||
void PPUTranslator::SetGpr(u32 r, Value* value)
|
||||
{
|
||||
RegStore<u64>(m_ir->CreateZExt(value, GetType<u64>()), m_gpr[r]);
|
||||
RegStore(m_ir->CreateZExt(value, GetType<u64>()), m_gpr[r]);
|
||||
}
|
||||
|
||||
Value* PPUTranslator::GetFpr(u32 r, u32 bits, bool as_int)
|
||||
{
|
||||
const auto value = RegLoad<f64>(m_fpr[r]);
|
||||
const auto value = RegLoad(m_fpr[r]);
|
||||
|
||||
if (!as_int && bits == 64)
|
||||
{
|
||||
|
|
@ -3878,16 +3879,12 @@ void PPUTranslator::SetFpr(u32 r, Value* val)
|
|||
val->getType() == GetType<s64>() ? m_ir->CreateBitCast(val, GetType<f64>()) :
|
||||
val->getType() == GetType<f32>() ? m_ir->CreateFPExt(val, GetType<f64>()) : val;
|
||||
|
||||
RegStore<f64>(f64_val, m_fpr[r]);
|
||||
RegStore(f64_val, m_fpr[r]);
|
||||
}
|
||||
|
||||
Value* PPUTranslator::GetVr(u32 vr, VrType type)
|
||||
{
|
||||
RegInit<u32[4]>(m_vr[vr]);
|
||||
|
||||
m_reads[&m_vr[vr] - m_locals] = true;
|
||||
|
||||
const auto value = m_ir->CreateAlignedLoad(m_vr[vr], 16);
|
||||
const auto value = RegLoad(m_vr[vr]);
|
||||
|
||||
switch (type)
|
||||
{
|
||||
|
|
@ -3903,10 +3900,6 @@ Value* PPUTranslator::GetVr(u32 vr, VrType type)
|
|||
|
||||
void PPUTranslator::SetVr(u32 vr, Value* value)
|
||||
{
|
||||
RegInit<u32[4]>(m_vr[vr]);
|
||||
|
||||
m_writes[&m_vr[vr] - m_locals] = true;
|
||||
|
||||
const auto type = value->getType();
|
||||
const auto size = type->getPrimitiveSizeInBits();
|
||||
|
||||
|
|
@ -3924,17 +3917,17 @@ void PPUTranslator::SetVr(u32 vr, Value* value)
|
|||
}
|
||||
}
|
||||
|
||||
m_ir->CreateAlignedStore(m_ir->CreateBitCast(value, GetType<u32[4]>()), m_vr[vr], 16);
|
||||
RegStore(m_ir->CreateBitCast(value, GetType<u32[4]>()), m_vr[vr]);
|
||||
}
|
||||
|
||||
Value* PPUTranslator::GetCrb(u32 crb)
|
||||
{
|
||||
return RegLoad<bool>(m_cr[crb]);
|
||||
return RegLoad(m_cr[crb]);
|
||||
}
|
||||
|
||||
void PPUTranslator::SetCrb(u32 crb, Value* value)
|
||||
{
|
||||
RegStore<bool>(value, m_cr[crb]);
|
||||
RegStore(value, m_cr[crb]);
|
||||
}
|
||||
|
||||
void PPUTranslator::SetCrField(u32 group, Value* lt, Value* gt, Value* eq, Value* so)
|
||||
|
|
@ -3942,7 +3935,7 @@ void PPUTranslator::SetCrField(u32 group, Value* lt, Value* gt, Value* eq, Value
|
|||
SetCrb(group * 4 + 0, lt ? lt : GetUndef<bool>());
|
||||
SetCrb(group * 4 + 1, gt ? gt : GetUndef<bool>());
|
||||
SetCrb(group * 4 + 2, eq ? eq : GetUndef<bool>());
|
||||
SetCrb(group * 4 + 3, so ? so : RegLoad<bool>(m_so));
|
||||
SetCrb(group * 4 + 3, so ? so : RegLoad(m_so));
|
||||
}
|
||||
|
||||
void PPUTranslator::SetCrFieldSignedCmp(u32 n, Value* a, Value* b)
|
||||
|
|
@ -4039,7 +4032,7 @@ Value* PPUTranslator::GetFPSCRBit(u32 n)
|
|||
}
|
||||
|
||||
// Get bit
|
||||
const auto value = RegLoad<bool>(m_fc[n]);
|
||||
const auto value = RegLoad(m_fc[n]);
|
||||
|
||||
//if (n == 0 || (n >= 3 && n <= 12) || (n >= 21 && n <= 23))
|
||||
//{
|
||||
|
|
@ -4072,28 +4065,28 @@ void PPUTranslator::SetFPSCRBit(u32 n, Value* value, bool update_fx)
|
|||
//if (n >= 30) CompilationError("SetFPSCRBit: RN bit");
|
||||
|
||||
// Store the bit
|
||||
RegStore<bool>(value, m_fc[n]);
|
||||
RegStore(value, m_fc[n]);
|
||||
}
|
||||
|
||||
Value* PPUTranslator::GetCarry()
|
||||
{
|
||||
return RegLoad<bool>(m_ca);
|
||||
return RegLoad(m_ca);
|
||||
}
|
||||
|
||||
void PPUTranslator::SetCarry(Value* bit)
|
||||
{
|
||||
RegStore<bool>(bit, m_ca);
|
||||
RegStore(bit, m_ca);
|
||||
}
|
||||
|
||||
void PPUTranslator::SetOverflow(Value* bit)
|
||||
{
|
||||
RegStore<bool>(bit, m_ov);
|
||||
RegStore<bool>(m_ir->CreateOr(RegLoad<bool>(m_so), bit), m_so);
|
||||
RegStore(bit, m_ov);
|
||||
RegStore(m_ir->CreateOr(RegLoad(m_so), bit), m_so);
|
||||
}
|
||||
|
||||
void PPUTranslator::SetSat(Value* bit)
|
||||
{
|
||||
RegStore<bool>(m_ir->CreateOr(RegLoad<bool>(m_sat), bit), m_sat);
|
||||
RegStore(m_ir->CreateOr(RegLoad(m_sat), bit), m_sat);
|
||||
}
|
||||
|
||||
Value* PPUTranslator::CheckTrapCondition(u32 to, Value* left, Value* right)
|
||||
|
|
@ -4121,10 +4114,10 @@ Value* PPUTranslator::CheckBranchCondition(u32 bo, u32 bi)
|
|||
const bool bo3 = (bo & 0x02) != 0;
|
||||
|
||||
// Decrement counter if necessary
|
||||
const auto ctr = bo2 ? nullptr : m_ir->CreateSub(RegLoad<u64>(m_ctr), m_ir->getInt64(1));
|
||||
const auto ctr = bo2 ? nullptr : m_ir->CreateSub(RegLoad(m_ctr), m_ir->getInt64(1));
|
||||
|
||||
// Store counter if necessary
|
||||
if (ctr) RegStore<u64>(ctr, m_ctr);
|
||||
if (ctr) RegStore(ctr, m_ctr);
|
||||
|
||||
// Generate counter condition
|
||||
const auto use_ctr = bo2 ? nullptr : m_ir->CreateICmp(bo3 ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE, ctr, m_ir->getInt64(0));
|
||||
|
|
|
|||
|
|
@ -150,59 +150,30 @@ class PPUTranslator final //: public CPUTranslator
|
|||
// Thread context struct
|
||||
llvm::StructType* m_thread_type;
|
||||
|
||||
llvm::Value* m_globals[169];
|
||||
llvm::Value* m_locals[169];
|
||||
llvm::Value** const m_gpr = m_locals + 0;
|
||||
llvm::Value** const m_fpr = m_locals + 32;
|
||||
llvm::Value** const m_vr = m_locals + 64;
|
||||
llvm::Value** const m_cr = m_locals + 96;
|
||||
llvm::Value** const m_fc = m_locals + 128;
|
||||
|
||||
std::array<bool, 169> m_writes;
|
||||
std::array<bool, 169> m_reads;
|
||||
llvm::Value* m_globals[173];
|
||||
llvm::Value* m_locals[173];
|
||||
llvm::Value** const m_gpr = m_locals + 3;
|
||||
llvm::Value** const m_fpr = m_locals + 35;
|
||||
llvm::Value** const m_vr = m_locals + 67;
|
||||
llvm::Value** const m_cr = m_locals + 99;
|
||||
llvm::Value** const m_fc = m_locals + 131; // FPSCR bits (used partially)
|
||||
|
||||
#define DEF_VALUE(loc, glb, pos)\
|
||||
llvm::Value*& loc = m_locals[pos];\
|
||||
llvm::Value*& glb = m_globals[pos];
|
||||
|
||||
DEF_VALUE(m_lr, m_g_lr, 160);
|
||||
DEF_VALUE(m_ctr, m_g_ctr, 161); // CTR register (counter)
|
||||
DEF_VALUE(m_vrsave, m_g_vrsave, 162);
|
||||
DEF_VALUE(m_so, m_g_so, 163); // XER.SO bit, summary overflow
|
||||
DEF_VALUE(m_ov, m_g_ov, 164); // XER.OV bit, overflow flag
|
||||
DEF_VALUE(m_ca, m_g_ca, 165); // XER.CA bit, carry flag
|
||||
DEF_VALUE(m_cnt, m_g_cnt, 166);
|
||||
DEF_VALUE(m_nj, m_g_nj, 167); // VSCR.NJ bit, non-Java mode
|
||||
DEF_VALUE(m_sat, m_g_sat, 168); // VSCR.SAT bit, sticky saturation flag
|
||||
DEF_VALUE(m_lr, m_g_lr, 163); // LR, Link Register
|
||||
DEF_VALUE(m_ctr, m_g_ctr, 164); // CTR, Counter Register
|
||||
DEF_VALUE(m_vrsave, m_g_vrsave, 165);
|
||||
DEF_VALUE(m_cia, m_g_cia, 166);
|
||||
DEF_VALUE(m_so, m_g_so, 167); // XER.SO bit, summary overflow
|
||||
DEF_VALUE(m_ov, m_g_ov, 168); // XER.OV bit, overflow flag
|
||||
DEF_VALUE(m_ca, m_g_ca, 169); // XER.CA bit, carry flag
|
||||
DEF_VALUE(m_cnt, m_g_cnt, 170); // XER.CNT
|
||||
DEF_VALUE(m_sat, m_g_sat, 171); // VSCR.SAT bit, sticky saturation flag
|
||||
DEF_VALUE(m_nj, m_g_nj, 172); // VSCR.NJ bit, non-Java mode
|
||||
|
||||
#undef DEF_VALUE
|
||||
|
||||
template <typename T>
|
||||
void RegInit(llvm::Value*& local)
|
||||
{
|
||||
if (!local)
|
||||
{
|
||||
local = new llvm::AllocaInst(GetType<T>(), nullptr, sizeof(T));
|
||||
m_entry->getInstList().push_back(llvm::cast<llvm::Instruction>(local));
|
||||
}
|
||||
}
|
||||
|
||||
template <typename T>
|
||||
llvm::Value* RegLoad(llvm::Value*& local)
|
||||
{
|
||||
RegInit<T>(local);
|
||||
m_reads.at(&local - m_locals) = true;
|
||||
return m_ir->CreateLoad(local);
|
||||
}
|
||||
|
||||
template <typename T>
|
||||
void RegStore(llvm::Value* value, llvm::Value*& local)
|
||||
{
|
||||
RegInit<T>(local);
|
||||
m_writes.at(&local - m_locals) = true;
|
||||
m_ir->CreateStore(value, local);
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
// Change integer size for integer or integer vector type (by 2^degree)
|
||||
|
|
@ -220,6 +191,15 @@ public:
|
|||
// Emit function call
|
||||
void CallFunction(u64 target, llvm::Value* indirect = nullptr);
|
||||
|
||||
// Initialize global for writing
|
||||
llvm::Value* RegInit(llvm::Value*& local);
|
||||
|
||||
// Load last register value
|
||||
llvm::Value* RegLoad(llvm::Value*& local);
|
||||
|
||||
// Store register value locally
|
||||
void RegStore(llvm::Value* value, llvm::Value*& local);
|
||||
|
||||
// Write global registers
|
||||
void FlushRegisters();
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue