mirror of
https://github.com/RPCS3/rpcs3.git
synced 2025-04-22 12:35:21 +00:00
Implement more instructions in the PPU LLVM recompiler
This commit is contained in:
S Gopal Rajagopal
parent
5934132b55
commit
d92344f383
3 changed files with 317 additions and 108 deletions
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@ -284,7 +284,7 @@ void Compiler::Decode(const u32 code) {
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}
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void Compiler::NULL_OP() {
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InterpreterCall("NULL_OP", &PPUInterpreter::NULL_OP);
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CompilationError("NULL_OP");
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}
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void Compiler::NOP() {
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@ -292,11 +292,11 @@ void Compiler::NOP() {
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}
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void Compiler::TDI(u32 to, u32 ra, s32 simm16) {
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InterpreterCall("TDI", &PPUInterpreter::TDI, to, ra, simm16);
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CompilationError("TDI");
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}
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void Compiler::TWI(u32 to, u32 ra, s32 simm16) {
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InterpreterCall("TWI", &PPUInterpreter::TWI, to, ra, simm16);
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CompilationError("TWI");
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}
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void Compiler::MFVSCR(u32 vd) {
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@ -1298,35 +1298,67 @@ void Compiler::VREFP(u32 vd, u32 vb) {
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}
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void Compiler::VRFIM(u32 vd, u32 vb) {
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InterpreterCall("VRFIM", &PPUInterpreter::VRFIM, vd, vb);
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auto vb_v4f32 = GetVrAsFloatVec(vb);
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auto res_v4f32 = m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::floor, VectorType::get(m_ir_builder->getFloatTy(), 4)), vb_v4f32);
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SetVr(vd, res_v4f32);
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}
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void Compiler::VRFIN(u32 vd, u32 vb) {
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InterpreterCall("VRFIN", &PPUInterpreter::VRFIN, vd, vb);
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auto vb_v4f32 = GetVrAsFloatVec(vb);
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auto res_v4f32 = m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::nearbyint, VectorType::get(m_ir_builder->getFloatTy(), 4)), vb_v4f32);
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SetVr(vd, res_v4f32);
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}
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void Compiler::VRFIP(u32 vd, u32 vb) {
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InterpreterCall("VRFIP", &PPUInterpreter::VRFIP, vd, vb);
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auto vb_v4f32 = GetVrAsFloatVec(vb);
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auto res_v4f32 = m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::ceil, VectorType::get(m_ir_builder->getFloatTy(), 4)), vb_v4f32);
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SetVr(vd, res_v4f32);
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}
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void Compiler::VRFIZ(u32 vd, u32 vb) {
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InterpreterCall("VRFIZ", &PPUInterpreter::VRFIZ, vd, vb);
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auto vb_v4f32 = GetVrAsFloatVec(vb);
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auto res_v4f32 = m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::trunc, VectorType::get(m_ir_builder->getFloatTy(), 4)), vb_v4f32);
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SetVr(vd, res_v4f32);
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}
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void Compiler::VRLB(u32 vd, u32 va, u32 vb) {
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InterpreterCall("VRLB", &PPUInterpreter::VRLB, vd, va, vb);
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auto va_v16i8 = GetVrAsIntVec(va, 8);
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auto vb_v16i8 = GetVrAsIntVec(vb, 8);
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vb_v16i8 = m_ir_builder->CreateAnd(vb_v16i8, m_ir_builder->CreateVectorSplat(16, m_ir_builder->getInt8(7)));
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auto tmp1_v16i8 = m_ir_builder->CreateShl(va_v16i8, vb_v16i8);
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vb_v16i8 = m_ir_builder->CreateSub(m_ir_builder->CreateVectorSplat(16, m_ir_builder->getInt8(8)), vb_v16i8);
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auto tmp2_v16i8 = m_ir_builder->CreateLShr(va_v16i8, vb_v16i8);
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auto res_v16i8 = m_ir_builder->CreateOr(tmp1_v16i8, tmp2_v16i8);
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SetVr(vd, res_v16i8);
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}
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void Compiler::VRLH(u32 vd, u32 va, u32 vb) {
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InterpreterCall("VRLH", &PPUInterpreter::VRLH, vd, va, vb);
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auto va_v8i16 = GetVrAsIntVec(va, 16);
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auto vb_v8i16 = GetVrAsIntVec(vb, 16);
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vb_v8i16 = m_ir_builder->CreateAnd(vb_v8i16, m_ir_builder->CreateVectorSplat(8, m_ir_builder->getInt16(0xF)));
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auto tmp1_v8i16 = m_ir_builder->CreateShl(va_v8i16, vb_v8i16);
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vb_v8i16 = m_ir_builder->CreateSub(m_ir_builder->CreateVectorSplat(8, m_ir_builder->getInt16(0x10)), vb_v8i16);
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auto tmp2_v8i16 = m_ir_builder->CreateLShr(va_v8i16, vb_v8i16);
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auto res_v8i16 = m_ir_builder->CreateOr(tmp1_v8i16, tmp2_v8i16);
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SetVr(vd, res_v8i16);
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}
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void Compiler::VRLW(u32 vd, u32 va, u32 vb) {
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InterpreterCall("VRLW", &PPUInterpreter::VRLW, vd, va, vb);
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auto va_v4i32 = GetVrAsIntVec(va, 32);
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auto vb_v4i32 = GetVrAsIntVec(vb, 32);
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vb_v4i32 = m_ir_builder->CreateAnd(vb_v4i32, m_ir_builder->CreateVectorSplat(4, m_ir_builder->getInt32(0x1F)));
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auto tmp1_v4i32 = m_ir_builder->CreateShl(va_v4i32, vb_v4i32);
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vb_v4i32 = m_ir_builder->CreateSub(m_ir_builder->CreateVectorSplat(4, m_ir_builder->getInt32(0x20)), vb_v4i32);
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auto tmp2_v4i32 = m_ir_builder->CreateLShr(va_v4i32, vb_v4i32);
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auto res_v4i32 = m_ir_builder->CreateOr(tmp1_v4i32, tmp2_v4i32);
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SetVr(vd, res_v4i32);
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}
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void Compiler::VRSQRTEFP(u32 vd, u32 vb) {
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InterpreterCall("VRSQRTEFP", &PPUInterpreter::VRSQRTEFP, vd, vb);
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auto vb_v4f32 = GetVrAsFloatVec(vb);
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auto res_v4f32 = m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::sqrt, VectorType::get(m_ir_builder->getFloatTy(), 4)), vb_v4f32);
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res_v4f32 = m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::x86_sse_rcp_ps), res_v4f32);
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SetVr(vd, res_v4f32);
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}
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void Compiler::VSEL(u32 vd, u32 va, u32 vb, u32 vc) {
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@ -1832,7 +1864,8 @@ void Compiler::CRXOR(u32 crbd, u32 crba, u32 crbb) {
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}
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void Compiler::DCBI(u32 ra, u32 rb) {
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InterpreterCall("DCBI", &PPUInterpreter::DCBI, ra, rb);
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// TODO: See if this can be translated to cache flush
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m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::donothing));
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}
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void Compiler::CRNAND(u32 crbd, u32 crba, u32 crbb) {
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@ -2125,7 +2158,7 @@ void Compiler::CMP(u32 crfd, u32 l, u32 ra, u32 rb) {
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}
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void Compiler::TW(u32 to, u32 ra, u32 rb) {
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InterpreterCall("TW", &PPUInterpreter::TW, to, ra, rb);
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CompilationError("TW");
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}
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void Compiler::LVSL(u32 vd, u32 ra, u32 rb) {
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@ -2506,7 +2539,7 @@ void Compiler::ANDC(u32 ra, u32 rs, u32 rb, bool rc) {
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}
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void Compiler::TD(u32 to, u32 ra, u32 rb) {
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InterpreterCall("TD", &PPUInterpreter::TD, to, ra, rb);
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CompilationError("TD");
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}
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void Compiler::LVEWX(u32 vd, u32 ra, u32 rb) {
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@ -2669,11 +2702,52 @@ void Compiler::STVEBX(u32 vs, u32 ra, u32 rb) {
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}
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void Compiler::SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) {
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InterpreterCall("SUBFE", &PPUInterpreter::SUBFE, rd, ra, rb, oe, rc);
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auto ca_i64 = GetXerCa();
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auto ra_i64 = GetGpr(ra);
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auto rb_i64 = GetGpr(rb);
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ra_i64 = m_ir_builder->CreateNot(ra_i64);
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auto res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), ra_i64, ca_i64);
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auto res_i64 = m_ir_builder->CreateExtractValue(res_s, {0});
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auto carry1_i1 = m_ir_builder->CreateExtractValue(res_s, {1});
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res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), res_i64, rb_i64);
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res_i64 = m_ir_builder->CreateExtractValue(res_s, {0});
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auto carry2_i1 = m_ir_builder->CreateExtractValue(res_s, {1});
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auto carry_i1 = m_ir_builder->CreateOr(carry1_i1, carry2_i1);
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SetGpr(rd, res_i64);
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SetXerCa(carry_i1);
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if (rc) {
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SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0));
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}
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if (oe) {
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// TODO: Implement this
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}
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//InterpreterCall("SUBFE", &PPUInterpreter::SUBFE, rd, ra, rb, oe, rc);
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}
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void Compiler::ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) {
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InterpreterCall("ADDE", &PPUInterpreter::ADDE, rd, ra, rb, oe, rc);
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auto ca_i64 = GetXerCa();
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auto ra_i64 = GetGpr(ra);
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auto rb_i64 = GetGpr(rb);
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auto res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), ra_i64, ca_i64);
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auto res_i64 = m_ir_builder->CreateExtractValue(res_s, {0});
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auto carry1_i1 = m_ir_builder->CreateExtractValue(res_s, {1});
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res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), res_i64, rb_i64);
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res_i64 = m_ir_builder->CreateExtractValue(res_s, {0});
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auto carry2_i1 = m_ir_builder->CreateExtractValue(res_s, {1});
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auto carry_i1 = m_ir_builder->CreateOr(carry1_i1, carry2_i1);
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SetGpr(rd, res_i64);
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SetXerCa(carry_i1);
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if (rc) {
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SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0));
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}
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if (oe) {
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// TODO: Implement this
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}
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//InterpreterCall("ADDE", &PPUInterpreter::ADDE, rd, ra, rb, oe, rc);
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}
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void Compiler::MTOCRF(u32 l, u32 crm, u32 rs) {
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@ -2793,7 +2867,19 @@ void Compiler::ADDZE(u32 rd, u32 ra, u32 oe, bool rc) {
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}
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void Compiler::SUBFZE(u32 rd, u32 ra, u32 oe, bool rc) {
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InterpreterCall("SUBFZE", &PPUInterpreter::SUBFZE, rd, ra, oe, rc);
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auto ra_i64 = GetGpr(ra);
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ra_i64 = m_ir_builder->CreateNot(ra_i64);
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auto ca_i64 = GetXerCa();
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auto res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), ra_i64, ca_i64);
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auto res_i64 = m_ir_builder->CreateExtractValue(res_s, {0});
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auto carry_i1 = m_ir_builder->CreateExtractValue(res_s, {1});
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SetGpr(rd, res_i64);
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SetXerCa(carry_i1);
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if (rc) {
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SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0));
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}
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//InterpreterCall("SUBFZE", &PPUInterpreter::SUBFZE, rd, ra, oe, rc);
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}
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void Compiler::STDCX_(u32 rs, u32 ra, u32 rb) {
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@ -2824,7 +2910,27 @@ void Compiler::STVX(u32 vs, u32 ra, u32 rb) {
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}
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void Compiler::SUBFME(u32 rd, u32 ra, u32 oe, bool rc) {
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InterpreterCall("SUBFME", &PPUInterpreter::SUBFME, rd, ra, oe, rc);
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auto ca_i64 = GetXerCa();
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auto ra_i64 = GetGpr(ra);
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ra_i64 = m_ir_builder->CreateNot(ra_i64);
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auto res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), ra_i64, ca_i64);
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auto res_i64 = m_ir_builder->CreateExtractValue(res_s, {0});
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auto carry1_i1 = m_ir_builder->CreateExtractValue(res_s, {1});
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res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), res_i64, m_ir_builder->getInt64((s64)-1));
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res_i64 = m_ir_builder->CreateExtractValue(res_s, {0});
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auto carry2_i1 = m_ir_builder->CreateExtractValue(res_s, {1});
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auto carry_i1 = m_ir_builder->CreateOr(carry1_i1, carry2_i1);
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SetGpr(rd, res_i64);
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SetXerCa(carry_i1);
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if (rc) {
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SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0));
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}
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if (oe) {
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// TODO: Implement this
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}
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//InterpreterCall("SUBFME", &PPUInterpreter::SUBFME, rd, ra, oe, rc);
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}
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void Compiler::MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) {
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@ -2842,7 +2948,26 @@ void Compiler::MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) {
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}
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void Compiler::ADDME(u32 rd, u32 ra, u32 oe, bool rc) {
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InterpreterCall("ADDME", &PPUInterpreter::ADDME, rd, ra, oe, rc);
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auto ca_i64 = GetXerCa();
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auto ra_i64 = GetGpr(ra);
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auto res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), ra_i64, ca_i64);
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auto res_i64 = m_ir_builder->CreateExtractValue(res_s, {0});
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auto carry1_i1 = m_ir_builder->CreateExtractValue(res_s, {1});
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res_s = m_ir_builder->CreateCall2(Intrinsic::getDeclaration(m_module, Intrinsic::uadd_with_overflow, m_ir_builder->getInt64Ty()), res_i64, m_ir_builder->getInt64((s64)-1));
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res_i64 = m_ir_builder->CreateExtractValue(res_s, {0});
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auto carry2_i1 = m_ir_builder->CreateExtractValue(res_s, {1});
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auto carry_i1 = m_ir_builder->CreateOr(carry1_i1, carry2_i1);
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SetGpr(rd, res_i64);
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SetXerCa(carry_i1);
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if (rc) {
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SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0));
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}
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if (oe) {
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// TODO: Implement this
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}
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//InterpreterCall("ADDME", &PPUInterpreter::ADDME, rd, ra, oe, rc);
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}
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void Compiler::MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) {
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@ -2913,7 +3038,17 @@ void Compiler::LHZX(u32 rd, u32 ra, u32 rb) {
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}
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void Compiler::EQV(u32 ra, u32 rs, u32 rb, bool rc) {
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InterpreterCall("EQV", &PPUInterpreter::EQV, ra, rs, rb, rc);
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auto rs_i64 = GetGpr(rs);
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auto rb_i64 = GetGpr(rb);
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auto res_i64 = m_ir_builder->CreateXor(rs_i64, rb_i64);
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res_i64 = m_ir_builder->CreateNot(res_i64);
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SetGpr(ra, res_i64);
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if (rc) {
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SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0));
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}
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//InterpreterCall("EQV", &PPUInterpreter::EQV, ra, rs, rb, rc);
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}
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void Compiler::ECIWX(u32 rd, u32 ra, u32 rb) {
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@ -2991,7 +3126,8 @@ void Compiler::LWAX(u32 rd, u32 ra, u32 rb) {
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}
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void Compiler::DST(u32 ra, u32 rb, u32 strm, u32 t) {
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InterpreterCall("DST", &PPUInterpreter::DST, ra, rb, strm, t);
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// TODO: Revisit
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m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::donothing));
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}
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void Compiler::LHAX(u32 rd, u32 ra, u32 rb) {
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@ -3036,7 +3172,8 @@ void Compiler::LWAUX(u32 rd, u32 ra, u32 rb) {
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}
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void Compiler::DSTST(u32 ra, u32 rb, u32 strm, u32 t) {
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InterpreterCall("DSTST", &PPUInterpreter::DSTST, ra, rb, strm, t);
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// TODO: Revisit
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m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::donothing));
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}
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void Compiler::LHAUX(u32 rd, u32 ra, u32 rb) {
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@ -3063,7 +3200,16 @@ void Compiler::STHX(u32 rs, u32 ra, u32 rb) {
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}
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void Compiler::ORC(u32 ra, u32 rs, u32 rb, bool rc) {
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InterpreterCall("ORC", &PPUInterpreter::ORC, ra, rs, rb, rc);
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auto rs_i64 = GetGpr(rs);
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auto rb_i64 = GetGpr(rb);
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rb_i64 = m_ir_builder->CreateNot(rb_i64);
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auto res_i64 = m_ir_builder->CreateOr(rs_i64, rb_i64);
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SetGpr(ra, res_i64);
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if (rc) {
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SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0));
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}
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//InterpreterCall("ORC", &PPUInterpreter::ORC, ra, rs, rb, rc);
|
||||
}
|
||||
|
||||
void Compiler::ECOWX(u32 rs, u32 ra, u32 rb) {
|
||||
|
|
@ -3149,7 +3295,16 @@ void Compiler::MTSPR(u32 spr, u32 rs) {
|
|||
}
|
||||
|
||||
void Compiler::NAND(u32 ra, u32 rs, u32 rb, bool rc) {
|
||||
InterpreterCall("NAND", &PPUInterpreter::NAND, ra, rs, rb, rc);
|
||||
auto rs_i64 = GetGpr(rs);
|
||||
auto rb_i64 = GetGpr(rb);
|
||||
auto res_i64 = m_ir_builder->CreateAnd(rs_i64, rb_i64);
|
||||
res_i64 = m_ir_builder->CreateNot(res_i64);
|
||||
SetGpr(ra, res_i64);
|
||||
|
||||
if (rc) {
|
||||
SetCrFieldSignedCmp(0, res_i64, m_ir_builder->getInt64(0));
|
||||
}
|
||||
//InterpreterCall("NAND", &PPUInterpreter::NAND, ra, rs, rb, rc);
|
||||
}
|
||||
|
||||
void Compiler::STVXL(u32 vs, u32 ra, u32 rb) {
|
||||
|
|
@ -3537,7 +3692,8 @@ void Compiler::LVRXL(u32 vd, u32 ra, u32 rb) {
|
|||
}
|
||||
|
||||
void Compiler::DSS(u32 strm, u32 a) {
|
||||
InterpreterCall("DSS", &PPUInterpreter::DSS, strm, a);
|
||||
// TODO: Revisit
|
||||
m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::donothing));
|
||||
}
|
||||
|
||||
void Compiler::SRAWI(u32 ra, u32 rs, u32 sh, bool rc) {
|
||||
|
|
@ -3661,7 +3817,8 @@ void Compiler::EXTSW(u32 ra, u32 rs, bool rc) {
|
|||
}
|
||||
|
||||
void Compiler::ICBI(u32 ra, u32 rs) {
|
||||
InterpreterCall("ICBI", &PPUInterpreter::ICBI, ra, rs);
|
||||
// TODO: Revisit
|
||||
m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::donothing));
|
||||
}
|
||||
|
||||
void Compiler::DCBZ(u32 ra, u32 rb) {
|
||||
|
|
@ -4050,7 +4207,12 @@ void Compiler::FSQRTS(u32 frd, u32 frb, bool rc) {
|
|||
}
|
||||
|
||||
void Compiler::FRES(u32 frd, u32 frb, bool rc) {
|
||||
InterpreterCall("FRES", &PPUInterpreter::FRES, frd, frb, rc);
|
||||
auto rb_f64 = GetFpr(frb);
|
||||
auto res_f64 = m_ir_builder->CreateFDiv(ConstantFP::get(m_ir_builder->getDoubleTy(), 1.0), rb_f64);
|
||||
SetFpr(frd, res_f64);
|
||||
|
||||
// TODO: Set flags
|
||||
//InterpreterCall("FRES", &PPUInterpreter::FRES, frd, frb, rc);
|
||||
}
|
||||
|
||||
void Compiler::FMULS(u32 frd, u32 fra, u32 frc, bool rc) {
|
||||
|
|
@ -4241,7 +4403,10 @@ void Compiler::FMUL(u32 frd, u32 fra, u32 frc, bool rc) {
|
|||
}
|
||||
|
||||
void Compiler::FRSQRTE(u32 frd, u32 frb, bool rc) {
|
||||
InterpreterCall("FRSQRTE", &PPUInterpreter::FRSQRTE, frd, frb, rc);
|
||||
auto rb_f64 = GetFpr(frb);
|
||||
auto res_f64 = (Value *)m_ir_builder->CreateCall(Intrinsic::getDeclaration(m_module, Intrinsic::sqrt, m_ir_builder->getDoubleTy()), rb_f64);
|
||||
res_f64 = m_ir_builder->CreateFDiv(ConstantFP::get(m_ir_builder->getDoubleTy(), 1.0), res_f64);
|
||||
SetFpr(frd, res_f64);
|
||||
}
|
||||
|
||||
void Compiler::FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {
|
||||
|
|
@ -4353,7 +4518,7 @@ void Compiler::FCFID(u32 frd, u32 frb, bool rc) {
|
|||
}
|
||||
|
||||
void Compiler::UNK(const u32 code, const u32 opcode, const u32 gcode) {
|
||||
//InterpreterCall("UNK", &PPUInterpreter::UNK, code, opcode, gcode);
|
||||
CompilationError(fmt::Format("Unknown/Illegal opcode! (0x%08x : 0x%x : 0x%x)", code, opcode, gcode));
|
||||
}
|
||||
|
||||
std::string Compiler::GetBasicBlockNameFromAddress(u32 address, const std::string & suffix) const {
|
||||
|
|
@ -5034,6 +5199,11 @@ llvm::Value * Compiler::IndirectCall(u32 address, Value * context_i64, bool is_f
|
|||
return m_ir_builder->CreateCall3(executable_ptr, m_state.args[CompileTaskState::Args::State], m_state.args[CompileTaskState::Args::Interpreter], context_i64);
|
||||
}
|
||||
|
||||
void Compiler::CompilationError(const std::string & error) {
|
||||
LOG_ERROR(PPU, "[0x%08X] %s", m_state.current_instruction_address, error.c_str());
|
||||
Emu.Pause();
|
||||
}
|
||||
|
||||
void Compiler::InitRotateMask() {
|
||||
for (u32 mb = 0; mb < 64; mb++) {
|
||||
for (u32 me = 0; me < 64; me++) {
|
||||
|
|
|
|||
|
|
@ -930,6 +930,9 @@ namespace ppu_recompiler_llvm {
|
|||
/// Excute a test
|
||||
void RunTest(const char * name, std::function<void()> test_case, std::function<void()> input, std::function<bool(std::string & msg)> check_result);
|
||||
|
||||
/// Handle compilation errors
|
||||
void CompilationError(const std::string & error);
|
||||
|
||||
/// A mask used in rotate instructions
|
||||
static u64 s_rotate_mask[64][64];
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
#include "llvm/Support/raw_ostream.h"
|
||||
#include "llvm/MC/MCDisassembler.h"
|
||||
|
||||
#define PPU_LLVM_RECOMPILER_UNIT_TESTS 1
|
||||
//#define PPU_LLVM_RECOMPILER_UNIT_TESTS 1
|
||||
|
||||
using namespace llvm;
|
||||
using namespace ppu_recompiler_llvm;
|
||||
|
|
@ -455,6 +455,14 @@ void Compiler::RunAllTests() {
|
|||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VPKUWUM, 0, 5, 0, 1, 2);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VPKUWUS, 0, 5, 0, 1, 2);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VREFP, 0, 5, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VRFIM, 0, 5, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VRFIN, 0, 5, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VRFIP, 0, 5, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VRFIZ, 0, 5, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VRLB, 0, 5, 0, 1, 2);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VRLH, 0, 5, 0, 1, 2);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VRLW, 0, 5, 0, 1, 2);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VRSQRTEFP, 0, 5, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VSEL, 0, 5, 0, 1, 2, 3);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VSL, 0, 5, 0, 1, 2);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(VSLB, 0, 5, 0, 1, 2);
|
||||
|
|
@ -509,7 +517,7 @@ void Compiler::RunAllTests() {
|
|||
// TODO: BCLR
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CRNOR, 0, 5, 0, 7, 3);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CRANDC, 0, 5, 5, 6, 7);
|
||||
// TODO: ISYNC
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ISYNC, 0, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CRXOR, 0, 5, 7, 7, 7);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CRNAND, 0, 5, 3, 4, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CRAND, 0, 5, 1, 2, 3);
|
||||
|
|
@ -539,100 +547,129 @@ void Compiler::RunAllTests() {
|
|||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(RLDIMI, 5, 5, 21, 22, 23, 43, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(RLDC_LR, 0, 5, 7, 8, 9, 12, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(RLDC_LR, 5, 5, 21, 22, 23, 43, 1, 1);
|
||||
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADD, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADD, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBF, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBF, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NEG, 0, 5, 7, 8, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NEG, 5, 5, 21, 22, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CMP, 0, 5, 3, 0, 9, 31);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CMP, 5, 5, 6, 1, 23, 14);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFC, 0, 5, 0, 1, 2, 0, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFC, 5, 5, 0, 1, 2, 0, true);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDC, 0, 5, 0, 1, 2, 0, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDC, 5, 5, 0, 1, 2, 0, true);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHDU, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHDU, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHWU, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHWU, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHD, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHD, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHW, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHW, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULLD, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULLD, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULLW, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULLW, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVD, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVD, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVDU, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVDU, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVW, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVW, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVWU, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVWU, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(AND, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(AND, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(OR, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(OR, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(XOR, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(XOR, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NOR, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NOR, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CMP, 0, 5, 3, 0, 9, 31);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CMP, 5, 5, 6, 1, 23, 14);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CMPL, 0, 5, 3, 0, 9, 31);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CMPL, 5, 5, 6, 1, 23, 14);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDC, 0, 5, 0, 1, 2, 0, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDC, 5, 5, 0, 1, 2, 0, true);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFC, 0, 5, 0, 1, 2, 0, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFC, 5, 5, 0, 1, 2, 0, true);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSB, 0, 5, 3, 5, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSB, 5, 5, 3, 5, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSH, 0, 5, 6, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSH, 5, 5, 6, 9, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSW, 0, 5, 25, 29, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSW, 5, 5, 25, 29, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTSPR, 0, 5, 0x20, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTSPR, 5, 5, 0x100, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTSPR, 10, 5, 0x120, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTSPR, 15, 5, 0x8, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MFSPR, 0, 5, 5, 0x20);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MFSPR, 5, 5, 5, 0x100);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MFSPR, 10, 5, 5, 0x120);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MFSPR, 15, 5, 5, 0x8);
|
||||
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAWI, 0, 5, 5, 6, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAWI, 5, 5, 5, 6, 12, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAWI, 10, 5, 5, 6, 22, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAWI, 15, 5, 5, 6, 31, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAW, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAW, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRADI1, 0, 5, 5, 6, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRADI1, 5, 5, 5, 6, 12, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRADI1, 10, 5, 5, 6, 48, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRADI1, 15, 5, 5, 6, 63, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAD, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAD, 5, 5, 5, 6, 7, 1);
|
||||
// TODO: MFOCRF
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SLW, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SLW, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRW, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRW, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SLD, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SLD, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRD, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRD, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CNTLZW, 0, 5, 5, 6, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CNTLZW, 5, 5, 5, 6, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SLD, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SLD, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(AND, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(AND, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CMPL, 0, 5, 3, 0, 9, 31);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CMPL, 5, 5, 6, 1, 23, 14);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBF, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBF, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CNTLZD, 0, 5, 5, 6, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(CNTLZD, 5, 5, 5, 6, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ANDC, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ANDC, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ISYNC, 0, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHD, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHD, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHW, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULHW, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NEG, 0, 5, 7, 8, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NEG, 5, 5, 21, 22, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NOR, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NOR, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFE, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFE, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDE, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDE, 5, 5, 21, 22, 23, 0, 1);
|
||||
// TODO: MTOCRF
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDZE, 0, 5, 7, 8, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDZE, 5, 5, 21, 22, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFZE, 0, 5, 7, 8, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFZE, 5, 5, 21, 22, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFME, 0, 5, 7, 8, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SUBFME, 5, 5, 21, 22, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULLD, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULLD, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDME, 0, 5, 7, 8, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADDME, 5, 5, 21, 22, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULLW, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MULLW, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADD, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ADD, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EQV, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EQV, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(XOR, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(XOR, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MFSPR, 0, 5, 5, 0x20);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MFSPR, 5, 5, 5, 0x100);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MFSPR, 10, 5, 5, 0x120);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MFSPR, 15, 5, 5, 0x8);
|
||||
// TODO: MFTB
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ORC, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(ORC, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(OR, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(OR, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVDU, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVDU, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVWU, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVWU, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTSPR, 0, 5, 0x20, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTSPR, 5, 5, 0x100, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTSPR, 10, 5, 0x120, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(MTSPR, 15, 5, 0x8, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NAND, 0, 5, 7, 8, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(NAND, 5, 5, 21, 22, 23, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVD, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVD, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVW, 0, 5, 7, 8, 9, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(DIVW, 5, 5, 21, 22, 23, 0, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRW, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRW, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRD, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRD, 5, 5, 5, 6, 7, 1);
|
||||
// TODO: SYNC
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAW, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAW, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAD, 0, 5, 5, 6, 7, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAD, 5, 5, 5, 6, 7, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAWI, 0, 5, 5, 6, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAWI, 5, 5, 5, 6, 12, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAWI, 10, 5, 5, 6, 22, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRAWI, 15, 5, 5, 6, 31, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRADI1, 0, 5, 5, 6, 0, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRADI1, 5, 5, 5, 6, 12, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRADI1, 10, 5, 5, 6, 48, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(SRADI1, 15, 5, 5, 6, 63, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EIEIO, 0, 5);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSH, 0, 5, 6, 9, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSH, 5, 5, 6, 9, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSB, 0, 5, 3, 5, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSB, 5, 5, 3, 5, 1);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSW, 0, 5, 25, 29, 0);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(EXTSW, 5, 5, 25, 29, 1);
|
||||
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FSQRT, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FDIVS, 0, 5, 0, 1, 2, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FSUBS, 0, 5, 0, 1, 2, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FADDS, 0, 5, 0, 1, 2, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FSQRTS, 0, 5, 0, 1, false);
|
||||
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FRES, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FMULS, 0, 5, 0, 1, 2, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FMADDS, 0, 5, 0, 1, 2, 3, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FMSUBS, 0, 5, 0, 1, 2, 3, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FNMSUBS, 0, 5, 0, 1, 2, 3, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FNMADDS, 0, 5, 0, 1, 2, 3, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FCTIW, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FDIV, 0, 5, 0, 1, 2, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FSUB, 0, 5, 0, 1, 2, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FADD, 0, 5, 0, 1, 2, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FSQRT, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FMUL, 0, 5, 0, 1, 2, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FRSQRTE, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FMSUB, 0, 5, 0, 1, 2, 3, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FMADD, 0, 5, 0, 1, 2, 3, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FNMSUB, 0, 5, 0, 1, 2, 3, false);
|
||||
|
|
@ -641,9 +678,8 @@ void Compiler::RunAllTests() {
|
|||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FMR, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FNABS, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FABS, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FCFID, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FCTID, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FCTIW, 0, 5, 0, 1, false);
|
||||
VERIFY_INSTRUCTION_AGAINST_INTERPRETER_USING_RANDOM_INPUT(FCFID, 0, 5, 0, 1, false);
|
||||
|
||||
PPUState input;
|
||||
input.SetRandom(0x10000);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue