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Merge pull request #793 from Nekotekina/master

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vm:: replacement 3
This commit is contained in:
Alexandro Sánchez Bach 2014-09-07 02:11:13 +02:00
commit ec9740e747
40 changed files with 562 additions and 813 deletions
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180
Utilities/BEType.h
View file

@ -1,5 +1,185 @@
#pragma once
#include <emmintrin.h>
union u128
{
struct
{
u64 hi;
u64 lo;
};
u64 _u64[2];
s64 _s64[2];
u32 _u32[4];
s32 _s32[4];
u16 _u16[8];
s16 _s16[8];
u8 _u8[16];
s8 _s8[16];
float _f[4];
double _d[2];
__m128 xmm;
class bit_array_128
{
u64 data[2];
public:
class bit_element
{
u64& data;
const u64 mask;
public:
bit_element(u64& data, const u64 mask)
: data(data)
, mask(mask)
{
}
__forceinline operator bool() const
{
return (data & mask) != 0;
}
__forceinline bit_element& operator = (const bool right)
{
if (right)
{
data |= mask;
}
else
{
data &= ~mask;
}
return *this;
}
__forceinline bit_element& operator = (const bit_element& right)
{
if (right)
{
data |= mask;
}
else
{
data &= ~mask;
}
return *this;
}
};
bit_element operator [] (u32 index)
{
assert(index < 128);
return bit_element(data[index / 64], 1ull << (index % 64));
}
const bool operator [] (u32 index) const
{
assert(index < 128);
return (data[index / 64] & (1ull << (index % 64))) != 0;
}
} _bit;
//operator u64() const { return _u64[0]; }
//operator u32() const { return _u32[0]; }
//operator u16() const { return _u16[0]; }
//operator u8() const { return _u8[0]; }
//operator bool() const { return _u64[0] != 0 || _u64[1] != 0; }
static u128 from128(u64 hi, u64 lo)
{
u128 ret = { hi, lo };
return ret;
}
static u128 from64(u64 src)
{
u128 ret = { 0, src };
return ret;
}
static u128 from32(u32 src)
{
u128 ret;
ret._u32[0] = src;
ret._u32[1] = 0;
ret._u32[2] = 0;
ret._u32[3] = 0;
return ret;
}
static u128 fromBit(u32 bit)
{
u128 ret;
ret._bit[bit] = true;
return ret;
}
void setBit(u32 bit)
{
_bit[bit] = true;
}
bool operator == (const u128& right) const
{
return (lo == right.lo) && (hi == right.hi);
}
bool operator != (const u128& right) const
{
return (lo != right.lo) || (hi != right.hi);
}
u128 operator | (const u128& right) const
{
return from128(hi | right.hi, lo | right.lo);
}
u128 operator & (const u128& right) const
{
return from128(hi & right.hi, lo & right.lo);
}
u128 operator ^ (const u128& right) const
{
return from128(hi ^ right.hi, lo ^ right.lo);
}
u128 operator ~ () const
{
return from128(~hi, ~lo);
}
void clear()
{
hi = lo = 0;
}
std::string to_hex() const
{
return fmt::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
}
std::string to_xyzw() const
{
return fmt::Format("x: %g y: %g z: %g w: %g", _f[3], _f[2], _f[1], _f[0]);
}
static __forceinline u128 byteswap(const u128 val)
{
u128 ret;
ret.lo = _byteswap_uint64(val.hi);
ret.hi = _byteswap_uint64(val.lo);
return ret;
}
};
#define re16(val) _byteswap_ushort(val)
#define re32(val) _byteswap_ulong(val)
#define re64(val) _byteswap_uint64(val)

4
rpcs3/Emu/ARMv7/ARMv7Decoder.h
View file

@ -21,8 +21,8 @@ public:
virtual u8 DecodeMemory(const u64 address)
{
using namespace ARMv7_opcodes;
const u16 code0 = Memory.PSV.Read16((u32)address);
const u16 code1 = Memory.PSV.Read16((u32)address + 2);
const u16 code0 = vm::psv::read16((u32)address);
const u16 code1 = vm::psv::read16((u32)address + 2);
switch(code0 >> 12) //15 - 12
{

4
rpcs3/Emu/ARMv7/ARMv7Interpreter.h
View file

@ -275,7 +275,7 @@ protected:
if(regs_list & mask)
{
CPU.SP -= 4;
Memory.PSV.Write32(CPU.SP, CPU.read_gpr(i));
vm::psv::write32(CPU.SP, CPU.read_gpr(i));
}
}
}
@ -286,7 +286,7 @@ protected:
{
if(regs_list & mask)
{
CPU.write_gpr(i, Memory.PSV.Read32(CPU.SP));
CPU.write_gpr(i, vm::psv::read32(CPU.SP));
CPU.SP += 4;
}
}

2
rpcs3/Emu/Cell/PPCDecoder.cpp
View file

@ -4,7 +4,7 @@
u8 PPCDecoder::DecodeMemory(const u64 address)
{
u32 instr = Memory.Read32(address);
u32 instr = vm::read32(address);
Decode(instr);
return sizeof(u32);

4
rpcs3/Emu/Cell/PPCThread.cpp
View file

@ -37,9 +37,9 @@ void PPCThread::InitStack()
/*
m_stack_point += m_stack_size - 0x10;
m_stack_point &= -0x10;
Memory.Write64(m_stack_point, 0);
vm::write64(m_stack_point, 0);
m_stack_point -= 0x60;
Memory.Write64(m_stack_point, m_stack_point + 0x60);
vm::write64(m_stack_point, m_stack_point + 0x60);
*/
}

224
rpcs3/Emu/Cell/PPUInterpreter.h
View file

@ -169,7 +169,7 @@ private:
void MFVSCR(u32 vd) //nf
{
CPU.VPR[vd].Clear();
CPU.VPR[vd].clear();
CPU.VPR[vd]._u32[0] = CPU.VSCR.VSCR;
}
void MTVSCR(u32 vb)
@ -771,10 +771,10 @@ private:
{
float result = CPU.VPR[vb]._f[w] * nScale;
if (result > S32_MAX)
CPU.VPR[vd]._s32[w] = (int)S32_MAX;
else if (result < S32_MIN)
CPU.VPR[vd]._s32[w] = (int)S32_MIN;
if (result > 0x7fffffff)
CPU.VPR[vd]._s32[w] = (int)0x7fffffff;
else if (result < -pow(2, 31))
CPU.VPR[vd]._s32[w] = (int)0x80000000;
else // C rounding = Round towards 0
CPU.VPR[vd]._s32[w] = (int)result;
}
@ -788,8 +788,8 @@ private:
// C rounding = Round towards 0
s64 result = (s64)(CPU.VPR[vb]._f[w] * nScale);
if (result > U32_MAX)
CPU.VPR[vd]._u32[w] = (u32)U32_MAX;
if (result > 0xffffffffu)
CPU.VPR[vd]._u32[w] = 0xffffffffu;
else if (result < 0)
CPU.VPR[vd]._u32[w] = 0;
else
@ -965,8 +965,8 @@ private:
}
void VMRGHB(u32 vd, u32 va, u32 vb)
{
VPR_reg VA = CPU.VPR[va];
VPR_reg VB = CPU.VPR[vb];
u128 VA = CPU.VPR[va];
u128 VB = CPU.VPR[vb];
for (uint h = 0; h < 8; h++)
{
CPU.VPR[vd]._u8[15 - h*2] = VA._u8[15 - h];
@ -975,8 +975,8 @@ private:
}
void VMRGHH(u32 vd, u32 va, u32 vb)
{
VPR_reg VA = CPU.VPR[va];
VPR_reg VB = CPU.VPR[vb];
u128 VA = CPU.VPR[va];
u128 VB = CPU.VPR[vb];
for (uint w = 0; w < 4; w++)
{
CPU.VPR[vd]._u16[7 - w*2] = VA._u16[7 - w];
@ -985,8 +985,8 @@ private:
}
void VMRGHW(u32 vd, u32 va, u32 vb)
{
VPR_reg VA = CPU.VPR[va];
VPR_reg VB = CPU.VPR[vb];
u128 VA = CPU.VPR[va];
u128 VB = CPU.VPR[vb];
for (uint d = 0; d < 2; d++)
{
CPU.VPR[vd]._u32[3 - d*2] = VA._u32[3 - d];
@ -1061,14 +1061,14 @@ private:
result += CPU.VPR[vc]._s32[w];
if (result > S32_MAX)
if (result > 0x7fffffff)
{
saturated = S32_MAX;
saturated = 0x7fffffff;
CPU.VSCR.SAT = 1;
}
else if (result < S32_MIN)
else if (result < (s64)(s32)0x80000000)
{
saturated = S32_MIN;
saturated = 0x80000000;
CPU.VSCR.SAT = 1;
}
else
@ -1121,9 +1121,9 @@ private:
result += CPU.VPR[vc]._u32[w];
if (result > U32_MAX)
if (result > 0xffffffffu)
{
saturated = U32_MAX;
saturated = 0xffffffff;
CPU.VSCR.SAT = 1;
}
else
@ -1578,7 +1578,7 @@ private:
{
u8 nShift = (CPU.VPR[vb]._u8[0] >> 3) & 0xf;
CPU.VPR[vd].Clear();
CPU.VPR[vd].clear();
for (u8 b = 0; b < 16 - nShift; b++)
{
@ -1711,7 +1711,7 @@ private:
{
u8 nShift = (CPU.VPR[vb]._u8[0] >> 3) & 0xf;
CPU.VPR[vd].Clear();
CPU.VPR[vd].clear();
for (u8 b = 0; b < 16 - nShift; b++)
{
@ -1867,7 +1867,7 @@ private:
}
void VSUMSWS(u32 vd, u32 va, u32 vb)
{
CPU.VPR[vd].Clear();
CPU.VPR[vd].clear();
s64 sum = CPU.VPR[vb]._s32[3];
@ -2300,8 +2300,8 @@ private:
{
//const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
//CPU.VPR[vd].Clear();
//CPU.VPR[vd]._u8[addr & 0xf] = Memory.Read8(addr);
CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
//CPU.VPR[vd]._u8[addr & 0xf] = vm::read8(addr);
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
}
void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
{
@ -2371,11 +2371,11 @@ private:
}
void LDX(u32 rd, u32 ra, u32 rb)
{
CPU.GPR[rd] = Memory.Read64(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
CPU.GPR[rd] = vm::read64(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
}
void LWZX(u32 rd, u32 ra, u32 rb)
{
CPU.GPR[rd] = Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
CPU.GPR[rd] = vm::read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
}
void SLW(u32 ra, u32 rs, u32 rb, bool rc)
{
@ -2449,8 +2449,8 @@ private:
{
//const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~1ULL;
//CPU.VPR[vd].Clear();
//(u16&)CPU.VPR[vd]._u8[addr & 0xf] = Memory.Read16(addr);
CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
//(u16&)CPU.VPR[vd]._u8[addr & 0xf] = vm::read16(addr);
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
}
void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
{
@ -2461,7 +2461,7 @@ private:
void LDUX(u32 rd, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
CPU.GPR[rd] = Memory.Read64(addr);
CPU.GPR[rd] = vm::read64(addr);
CPU.GPR[ra] = addr;
}
void DCBST(u32 ra, u32 rb)
@ -2472,7 +2472,7 @@ private:
void LWZUX(u32 rd, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
CPU.GPR[rd] = Memory.Read32(addr);
CPU.GPR[rd] = vm::read32(addr);
CPU.GPR[ra] = addr;
}
void CNTLZD(u32 ra, u32 rs, bool rc)
@ -2499,8 +2499,8 @@ private:
{
//const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL;
//CPU.VPR[vd].Clear();
//(u32&)CPU.VPR[vd]._u8[addr & 0xf] = Memory.Read32(addr);
CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
//(u32&)CPU.VPR[vd]._u8[addr & 0xf] = vm::read32(addr);
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
}
void MULHD(u32 rd, u32 ra, u32 rb, bool rc)
{
@ -2527,11 +2527,11 @@ private:
}
void LBZX(u32 rd, u32 ra, u32 rb)
{
CPU.GPR[rd] = Memory.Read8(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
CPU.GPR[rd] = vm::read8(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
}
void LVX(u32 vd, u32 ra, u32 rb)
{
CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
}
void NEG(u32 rd, u32 ra, u32 oe, bool rc)
{
@ -2544,7 +2544,7 @@ private:
//if(ra == 0 || ra == rd) throw "Bad instruction [LBZUX]";
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
CPU.GPR[rd] = Memory.Read8(addr);
CPU.GPR[rd] = vm::read8(addr);
CPU.GPR[ra] = addr;
}
void NOR(u32 ra, u32 rs, u32 rb, bool rc)
@ -2556,7 +2556,7 @@ private:
{
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
const u8 eb = addr & 0xf;
Memory.Write8(addr, CPU.VPR[vs]._u8[15 - eb]);
vm::write8(addr, CPU.VPR[vs]._u8[15 - eb]);
}
void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
{
@ -2627,7 +2627,7 @@ private:
}
void STDX(u32 rs, u32 ra, u32 rb)
{
Memory.Write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]);
vm::write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]);
}
void STWCX_(u32 rs, u32 ra, u32 rb)
{
@ -2645,31 +2645,31 @@ private:
}
void STWX(u32 rs, u32 ra, u32 rb)
{
Memory.Write32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u32)CPU.GPR[rs]);
vm::write32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u32)CPU.GPR[rs]);
}
void STVEHX(u32 vs, u32 ra, u32 rb)
{
const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~1ULL;
const u8 eb = (addr & 0xf) >> 1;
Memory.Write16(addr, CPU.VPR[vs]._u16[7 - eb]);
vm::write16(addr, CPU.VPR[vs]._u16[7 - eb]);
}
void STDUX(u32 rs, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write64(addr, CPU.GPR[rs]);
vm::write64(addr, CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void STWUX(u32 rs, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write32(addr, (u32)CPU.GPR[rs]);
vm::write32(addr, (u32)CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void STVEWX(u32 vs, u32 ra, u32 rb)
{
const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL;
const u8 eb = (addr & 0xf) >> 2;
Memory.Write32(addr, CPU.VPR[vs]._u32[3 - eb]);
vm::write32(addr, CPU.VPR[vs]._u32[3 - eb]);
}
void ADDZE(u32 rd, u32 ra, u32 oe, bool rc)
{
@ -2703,11 +2703,11 @@ private:
}
void STBX(u32 rs, u32 ra, u32 rb)
{
Memory.Write8((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u8)CPU.GPR[rs]);
vm::write8((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u8)CPU.GPR[rs]);
}
void STVX(u32 vs, u32 ra, u32 rb)
{
Memory.Write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]._u128);
vm::write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]);
}
void SUBFME(u32 rd, u32 ra, u32 oe, bool rc)
{
@ -2746,7 +2746,7 @@ private:
void STBUX(u32 rs, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write8(addr, (u8)CPU.GPR[rs]);
vm::write8(addr, (u8)CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
@ -2764,7 +2764,7 @@ private:
}
void LHZX(u32 rd, u32 ra, u32 rb)
{
CPU.GPR[rd] = Memory.Read16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
CPU.GPR[rd] = vm::read16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
}
void EQV(u32 ra, u32 rs, u32 rb, bool rc)
{
@ -2774,12 +2774,12 @@ private:
void ECIWX(u32 rd, u32 ra, u32 rb)
{
//HACK!
CPU.GPR[rd] = Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
CPU.GPR[rd] = vm::read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
}
void LHZUX(u32 rd, u32 ra, u32 rb)
{
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
CPU.GPR[rd] = Memory.Read16(addr);
CPU.GPR[rd] = vm::read16(addr);
CPU.GPR[ra] = addr;
}
void XOR(u32 ra, u32 rs, u32 rb, bool rc)
@ -2793,7 +2793,7 @@ private:
}
void LWAX(u32 rd, u32 ra, u32 rb)
{
CPU.GPR[rd] = (s64)(s32)Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
CPU.GPR[rd] = (s64)(s32)vm::read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
}
void DST(u32 ra, u32 rb, u32 strm, u32 t)
{
@ -2801,11 +2801,11 @@ private:
}
void LHAX(u32 rd, u32 ra, u32 rb)
{
CPU.GPR[rd] = (s64)(s16)Memory.Read16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
CPU.GPR[rd] = (s64)(s16)vm::read16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
}
void LVXL(u32 vd, u32 ra, u32 rb)
{
CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
}
void MFTB(u32 rd, u32 spr)
{
@ -2821,7 +2821,7 @@ private:
void LWAUX(u32 rd, u32 ra, u32 rb)
{
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
CPU.GPR[rd] = (s64)(s32)Memory.Read32(addr);
CPU.GPR[rd] = (s64)(s32)vm::read32(addr);
CPU.GPR[ra] = addr;
}
void DSTST(u32 ra, u32 rb, u32 strm, u32 t)
@ -2831,12 +2831,12 @@ private:
void LHAUX(u32 rd, u32 ra, u32 rb)
{
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
CPU.GPR[rd] = (s64)(s16)Memory.Read16(addr);
CPU.GPR[rd] = (s64)(s16)vm::read16(addr);
CPU.GPR[ra] = addr;
}
void STHX(u32 rs, u32 ra, u32 rb)
{
Memory.Write16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u16)CPU.GPR[rs]);
vm::write16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u16)CPU.GPR[rs]);
}
void ORC(u32 ra, u32 rs, u32 rb, bool rc)
{
@ -2846,12 +2846,12 @@ private:
void ECOWX(u32 rs, u32 ra, u32 rb)
{
//HACK!
Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u32)CPU.GPR[rs]);
vm::write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u32)CPU.GPR[rs]);
}
void STHUX(u32 rs, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write16(addr, (u16)CPU.GPR[rs]);
vm::write16(addr, (u16)CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void OR(u32 ra, u32 rs, u32 rb, bool rc)
@ -2906,7 +2906,7 @@ private:
}
void STVXL(u32 vs, u32 ra, u32 rb)
{
Memory.Write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]._u128);
vm::write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]);
}
void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
{
@ -2947,8 +2947,8 @@ private:
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
const u8 eb = addr & 0xf;
CPU.VPR[vd].Clear();
for (u32 i = 0; i < 16 - eb; ++i) CPU.VPR[vd]._u8[15 - i] = Memory.Read8(addr + i);
CPU.VPR[vd].clear();
for (u32 i = 0; i < 16 - eb; ++i) CPU.VPR[vd]._u8[15 - i] = vm::read8(addr + i);
}
void LDBRX(u32 rd, u32 ra, u32 rb)
{
@ -2964,7 +2964,7 @@ private:
}
void LFSX(u32 frd, u32 ra, u32 rb)
{
(u32&)CPU.FPR[frd] = Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
(u32&)CPU.FPR[frd] = vm::read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
CPU.FPR[frd] = (float&)CPU.FPR[frd];
}
void SRW(u32 ra, u32 rs, u32 rb, bool rc)
@ -2990,8 +2990,8 @@ private:
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
const u8 eb = addr & 0xf;
CPU.VPR[vd].Clear();
for (u32 i = 16 - eb; i < 16; ++i) CPU.VPR[vd]._u8[15 - i] = Memory.Read8(addr + i - 16);
CPU.VPR[vd].clear();
for (u32 i = 16 - eb; i < 16; ++i) CPU.VPR[vd]._u8[15 - i] = vm::read8(addr + i - 16);
}
void LSWI(u32 rd, u32 ra, u32 nb)
{
@ -3003,7 +3003,7 @@ private:
{
if (N > 3)
{
CPU.GPR[reg] = Memory.Read32(EA);
CPU.GPR[reg] = vm::read32(EA);
EA += 4;
N -= 4;
}
@ -3013,7 +3013,7 @@ private:
while (N > 0)
{
N = N - 1;
buf |= Memory.Read8(EA) <<(N*8) ;
buf |= vm::read8(EA) <<(N*8) ;
EA = EA + 1;
}
CPU.GPR[reg] = buf;
@ -3024,7 +3024,7 @@ private:
void LFSUX(u32 frd, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
(u64&)CPU.FPR[frd] = Memory.Read32(addr);
(u64&)CPU.FPR[frd] = vm::read32(addr);
CPU.FPR[frd] = (float&)CPU.FPR[frd];
CPU.GPR[ra] = addr;
}
@ -3034,12 +3034,12 @@ private:
}
void LFDX(u32 frd, u32 ra, u32 rb)
{
(u64&)CPU.FPR[frd] = Memory.Read64(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
(u64&)CPU.FPR[frd] = vm::read64(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]);
}
void LFDUX(u32 frd, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
(u64&)CPU.FPR[frd] = Memory.Read64(addr);
(u64&)CPU.FPR[frd] = vm::read64(addr);
CPU.GPR[ra] = addr;
}
void STVLX(u32 vs, u32 ra, u32 rb)
@ -3047,7 +3047,7 @@ private:
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
const u8 eb = addr & 0xf;
for (u32 i = 0; i < 16 - eb; ++i) Memory.Write8(addr + i, CPU.VPR[vs]._u8[15 - i]);
for (u32 i = 0; i < 16 - eb; ++i) vm::write8(addr + i, CPU.VPR[vs]._u8[15 - i]);
}
void STSWX(u32 rs, u32 ra, u32 rb)
{
@ -3059,19 +3059,19 @@ private:
}
void STFSX(u32 frs, u32 ra, u32 rb)
{
Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.FPR[frs].To32());
vm::write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.FPR[frs].To32());
}
void STVRX(u32 vs, u32 ra, u32 rb)
{
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
const u8 eb = addr & 0xf;
for (u32 i = 16 - eb; i < 16; ++i) Memory.Write8(addr + i - 16, CPU.VPR[vs]._u8[15 - i]);
for (u32 i = 16 - eb; i < 16; ++i) vm::write8(addr + i - 16, CPU.VPR[vs]._u8[15 - i]);
}
void STFSUX(u32 frs, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write32(addr, CPU.FPR[frs].To32());
vm::write32(addr, CPU.FPR[frs].To32());
CPU.GPR[ra] = addr;
}
void STSWI(u32 rd, u32 ra, u32 nb)
@ -3084,7 +3084,7 @@ private:
{
if (N > 3)
{
Memory.Write32(EA, (u32)CPU.GPR[reg]);
vm::write32(EA, (u32)CPU.GPR[reg]);
EA += 4;
N -= 4;
}
@ -3094,7 +3094,7 @@ private:
while (N > 0)
{
N = N - 1;
Memory.Write8(EA, (0xFF000000 & buf) >> 24);
vm::write8(EA, (0xFF000000 & buf) >> 24);
buf <<= 8;
EA = EA + 1;
}
@ -3104,12 +3104,12 @@ private:
}
void STFDX(u32 frs, u32 ra, u32 rb)
{
Memory.Write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u64&)CPU.FPR[frs]);
vm::write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u64&)CPU.FPR[frs]);
}
void STFDUX(u32 frs, u32 ra, u32 rb)
{
const u64 addr = CPU.GPR[ra] + CPU.GPR[rb];
Memory.Write64(addr, (u64&)CPU.FPR[frs]);
vm::write64(addr, (u64&)CPU.FPR[frs]);
CPU.GPR[ra] = addr;
}
void LVLXL(u32 vd, u32 ra, u32 rb)
@ -3117,8 +3117,8 @@ private:
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
const u8 eb = addr & 0xf;
CPU.VPR[vd].Clear();
for (u32 i = 0; i < 16 - eb; ++i) CPU.VPR[vd]._u8[15 - i] = Memory.Read8(addr + i);
CPU.VPR[vd].clear();
for (u32 i = 0; i < 16 - eb; ++i) CPU.VPR[vd]._u8[15 - i] = vm::read8(addr + i);
}
void LHBRX(u32 rd, u32 ra, u32 rb)
{
@ -3163,8 +3163,8 @@ private:
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
const u8 eb = addr & 0xf;
CPU.VPR[vd].Clear();
for (u32 i = 16 - eb; i < 16; ++i) CPU.VPR[vd]._u8[15 - i] = Memory.Read8(addr + i - 16);
CPU.VPR[vd].clear();
for (u32 i = 16 - eb; i < 16; ++i) CPU.VPR[vd]._u8[15 - i] = vm::read8(addr + i - 16);
}
void DSS(u32 strm, u32 a)
{
@ -3199,7 +3199,7 @@ private:
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
const u8 eb = addr & 0xf;
for (u32 i = 0; i < 16 - eb; ++i) Memory.Write8(addr + i, CPU.VPR[vs]._u8[15 - i]);
for (u32 i = 0; i < 16 - eb; ++i) vm::write8(addr + i, CPU.VPR[vs]._u8[15 - i]);
}
void STHBRX(u32 rs, u32 ra, u32 rb)
{
@ -3215,7 +3215,7 @@ private:
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
const u8 eb = addr & 0xf;
for (u32 i = 16 - eb; i < 16; ++i) Memory.Write8(addr + i - 16, CPU.VPR[vs]._u8[15 - i]);
for (u32 i = 16 - eb; i < 16; ++i) vm::write8(addr + i - 16, CPU.VPR[vs]._u8[15 - i]);
}
void EXTSB(u32 ra, u32 rs, bool rc)
{
@ -3224,7 +3224,7 @@ private:
}
void STFIWX(u32 frs, u32 ra, u32 rb)
{
Memory.Write32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u32&)CPU.FPR[frs]);
vm::write32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u32&)CPU.FPR[frs]);
}
void EXTSW(u32 ra, u32 rs, bool rc)
{
@ -3245,72 +3245,72 @@ private:
}
void LWZ(u32 rd, u32 ra, s32 d)
{
CPU.GPR[rd] = Memory.Read32(ra ? CPU.GPR[ra] + d : d);
CPU.GPR[rd] = vm::read32(ra ? CPU.GPR[ra] + d : d);
}
void LWZU(u32 rd, u32 ra, s32 d)
{
const u64 addr = CPU.GPR[ra] + d;
CPU.GPR[rd] = Memory.Read32(addr);
CPU.GPR[rd] = vm::read32(addr);
CPU.GPR[ra] = addr;
}
void LBZ(u32 rd, u32 ra, s32 d)
{
CPU.GPR[rd] = Memory.Read8(ra ? CPU.GPR[ra] + d : d);
CPU.GPR[rd] = vm::read8(ra ? CPU.GPR[ra] + d : d);
}
void LBZU(u32 rd, u32 ra, s32 d)
{
const u64 addr = CPU.GPR[ra] + d;
CPU.GPR[rd] = Memory.Read8(addr);
CPU.GPR[rd] = vm::read8(addr);
CPU.GPR[ra] = addr;
}
void STW(u32 rs, u32 ra, s32 d)
{
Memory.Write32(ra ? CPU.GPR[ra] + d : d, (u32)CPU.GPR[rs]);
vm::write32(ra ? CPU.GPR[ra] + d : d, (u32)CPU.GPR[rs]);
}
void STWU(u32 rs, u32 ra, s32 d)
{
const u64 addr = CPU.GPR[ra] + d;
Memory.Write32(addr, (u32)CPU.GPR[rs]);
vm::write32(addr, (u32)CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void STB(u32 rs, u32 ra, s32 d)
{
Memory.Write8(ra ? CPU.GPR[ra] + d : d, (u8)CPU.GPR[rs]);
vm::write8(ra ? CPU.GPR[ra] + d : d, (u8)CPU.GPR[rs]);
}
void STBU(u32 rs, u32 ra, s32 d)
{
const u64 addr = CPU.GPR[ra] + d;
Memory.Write8(addr, (u8)CPU.GPR[rs]);
vm::write8(addr, (u8)CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void LHZ(u32 rd, u32 ra, s32 d)
{
CPU.GPR[rd] = Memory.Read16(ra ? CPU.GPR[ra] + d : d);
CPU.GPR[rd] = vm::read16(ra ? CPU.GPR[ra] + d : d);
}
void LHZU(u32 rd, u32 ra, s32 d)
{
const u64 addr = CPU.GPR[ra] + d;
CPU.GPR[rd] = Memory.Read16(addr);
CPU.GPR[rd] = vm::read16(addr);
CPU.GPR[ra] = addr;
}
void LHA(u32 rd, u32 ra, s32 d)
{
CPU.GPR[rd] = (s64)(s16)Memory.Read16(ra ? CPU.GPR[ra] + d : d);
CPU.GPR[rd] = (s64)(s16)vm::read16(ra ? CPU.GPR[ra] + d : d);
}
void LHAU(u32 rd, u32 ra, s32 d)
{
const u64 addr = CPU.GPR[ra] + d;
CPU.GPR[rd] = (s64)(s16)Memory.Read16(addr);
CPU.GPR[rd] = (s64)(s16)vm::read16(addr);
CPU.GPR[ra] = addr;
}
void STH(u32 rs, u32 ra, s32 d)
{
Memory.Write16(ra ? CPU.GPR[ra] + d : d, (u16)CPU.GPR[rs]);
vm::write16(ra ? CPU.GPR[ra] + d : d, (u16)CPU.GPR[rs]);
}
void STHU(u32 rs, u32 ra, s32 d)
{
const u64 addr = CPU.GPR[ra] + d;
Memory.Write16(addr, (u16)CPU.GPR[rs]);
vm::write16(addr, (u16)CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void LMW(u32 rd, u32 ra, s32 d)
@ -3318,7 +3318,7 @@ private:
u64 addr = ra ? CPU.GPR[ra] + d : d;
for(u32 i=rd; i<32; ++i, addr += 4)
{
CPU.GPR[i] = Memory.Read32(addr);
CPU.GPR[i] = vm::read32(addr);
}
}
void STMW(u32 rs, u32 ra, s32 d)
@ -3326,65 +3326,65 @@ private:
u64 addr = ra ? CPU.GPR[ra] + d : d;
for(u32 i=rs; i<32; ++i, addr += 4)
{
Memory.Write32(addr, (u32)CPU.GPR[i]);
vm::write32(addr, (u32)CPU.GPR[i]);
}
}
void LFS(u32 frd, u32 ra, s32 d)
{
const u32 v = Memory.Read32(ra ? CPU.GPR[ra] + d : d);
const u32 v = vm::read32(ra ? CPU.GPR[ra] + d : d);
CPU.FPR[frd] = (float&)v;
}
void LFSU(u32 frd, u32 ra, s32 ds)
{
const u64 addr = CPU.GPR[ra] + ds;
const u32 v = Memory.Read32(addr);
const u32 v = vm::read32(addr);
CPU.FPR[frd] = (float&)v;
CPU.GPR[ra] = addr;
}
void LFD(u32 frd, u32 ra, s32 d)
{
(u64&)CPU.FPR[frd] = Memory.Read64(ra ? CPU.GPR[ra] + d : d);
(u64&)CPU.FPR[frd] = vm::read64(ra ? CPU.GPR[ra] + d : d);
}
void LFDU(u32 frd, u32 ra, s32 ds)
{
const u64 addr = CPU.GPR[ra] + ds;
(u64&)CPU.FPR[frd] = Memory.Read64(addr);
(u64&)CPU.FPR[frd] = vm::read64(addr);
CPU.GPR[ra] = addr;
}
void STFS(u32 frs, u32 ra, s32 d)
{
Memory.Write32(ra ? CPU.GPR[ra] + d : d, CPU.FPR[frs].To32());
vm::write32(ra ? CPU.GPR[ra] + d : d, CPU.FPR[frs].To32());
}
void STFSU(u32 frs, u32 ra, s32 d)
{
const u64 addr = CPU.GPR[ra] + d;
Memory.Write32(addr, CPU.FPR[frs].To32());
vm::write32(addr, CPU.FPR[frs].To32());
CPU.GPR[ra] = addr;
}
void STFD(u32 frs, u32 ra, s32 d)
{
Memory.Write64(ra ? CPU.GPR[ra] + d : d, (u64&)CPU.FPR[frs]);
vm::write64(ra ? CPU.GPR[ra] + d : d, (u64&)CPU.FPR[frs]);
}
void STFDU(u32 frs, u32 ra, s32 d)
{
const u64 addr = CPU.GPR[ra] + d;
Memory.Write64(addr, (u64&)CPU.FPR[frs]);
vm::write64(addr, (u64&)CPU.FPR[frs]);
CPU.GPR[ra] = addr;
}
void LD(u32 rd, u32 ra, s32 ds)
{
CPU.GPR[rd] = Memory.Read64(ra ? CPU.GPR[ra] + ds : ds);
CPU.GPR[rd] = vm::read64(ra ? CPU.GPR[ra] + ds : ds);
}
void LDU(u32 rd, u32 ra, s32 ds)
{
//if(ra == 0 || rt == ra) return;
const u64 addr = CPU.GPR[ra] + ds;
CPU.GPR[rd] = Memory.Read64(addr);
CPU.GPR[rd] = vm::read64(addr);
CPU.GPR[ra] = addr;
}
void LWA(u32 rd, u32 ra, s32 ds)
{
CPU.GPR[rd] = (s64)(s32)Memory.Read32(ra ? CPU.GPR[ra] + ds : ds);
CPU.GPR[rd] = (s64)(s32)vm::read32(ra ? CPU.GPR[ra] + ds : ds);
}
void FDIVS(u32 frd, u32 fra, u32 frb, bool rc)
{
@ -3487,13 +3487,13 @@ private:
}
void STD(u32 rs, u32 ra, s32 d)
{
Memory.Write64(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]);
vm::write64(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]);
}
void STDU(u32 rs, u32 ra, s32 ds)
{
//if(ra == 0 || rs == ra) return;
const u64 addr = CPU.GPR[ra] + ds;
Memory.Write64(addr, CPU.GPR[rs]);
vm::write64(addr, CPU.GPR[rs]);
CPU.GPR[ra] = addr;
}
void MTFSB1(u32 crbd, bool rc)
@ -3993,7 +3993,7 @@ private:
for(uint i=0; i<32; ++i) LOG_NOTICE(PPU, "r%d = 0x%llx", i, CPU.GPR[i]);
for(uint i=0; i<32; ++i) LOG_NOTICE(PPU, "f%d = %llf", i, CPU.FPR[i]);
for(uint i=0; i<32; ++i) LOG_NOTICE(PPU, "v%d = 0x%s [%s]", i, CPU.VPR[i].ToString(true).c_str(), CPU.VPR[i].ToString().c_str());
for(uint i=0; i<32; ++i) LOG_NOTICE(PPU, "v%d = 0x%s [%s]", i, CPU.VPR[i].to_hex().c_str(), CPU.VPR[i].to_xyzw().c_str());
LOG_NOTICE(PPU, "CR = 0x%08x", CPU.CR);
LOG_NOTICE(PPU, "LR = 0x%llx", CPU.LR);
LOG_NOTICE(PPU, "CTR = 0x%llx", CPU.CTR);

6
rpcs3/Emu/Cell/PPUThread.cpp
View file

@ -61,8 +61,8 @@ void PPUThread::AddArgv(const std::string& arg)
void PPUThread::InitRegs()
{
const u32 pc = Memory.Read32(entry);
const u32 rtoc = Memory.Read32(entry + 4);
const u32 pc = vm::read32(entry);
const u32 rtoc = vm::read32(entry + 4);
//ConLog.Write("entry = 0x%x", entry);
//ConLog.Write("rtoc = 0x%x", rtoc);
@ -219,7 +219,7 @@ int FPRdouble::Cmp(PPCdouble a, PPCdouble b)
u64 PPUThread::GetStackArg(s32 i)
{
return Memory.Read64(GPR[1] + 0x70 + 0x8 * (i - 9));
return vm::read64(GPR[1] + 0x70 + 0x8 * (i - 9));
}
u64 PPUThread::FastCall(u64 addr, u64 rtoc, u64 arg1, u64 arg2, u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7, u64 arg8)

57
rpcs3/Emu/Cell/PPUThread.h
View file

@ -468,59 +468,6 @@ struct FPRdouble
static int Cmp(PPCdouble a, PPCdouble b);
};
union VPR_reg
{
//__m128i _m128i;
u128 _u128;
s128 _s128;
u64 _u64[2];
s64 _s64[2];
u32 _u32[4];
s32 _s32[4];
u16 _u16[8];
s16 _s16[8];
u8 _u8[16];
s8 _s8[16];
float _f[4];
double _d[2];
VPR_reg() { Clear(); }
std::string ToString(bool hex = false) const
{
if(hex) return fmt::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
return fmt::Format("x: %g y: %g z: %g w: %g", _f[3], _f[2], _f[1], _f[0]);
}
u8 GetBit(u8 bit)
{
if(bit < 64) return (_u64[0] >> bit) & 0x1;
return (_u64[1] >> (bit - 64)) & 0x1;
}
void SetBit(u8 bit, u8 value)
{
if(bit < 64)
{
_u64[0] &= ~(1 << bit);
_u64[0] |= (value & 0x1) << bit;
return;
}
bit -= 64;
_u64[1] &= ~(1 << bit);
_u64[1] |= (value & 0x1) << bit;
}
void Clear() { _u64[1] = _u64[0] = 0; }
};
static const s32 MAX_INT_VALUE = 0x7fffffff;
class PPUThread : public PPCThread
{
public:
@ -530,7 +477,7 @@ public:
PPCdouble FPR[32]; //Floating Point Register
FPSCRhdr FPSCR; //Floating Point Status and Control Register
u64 GPR[32]; //General-Purpose Register
VPR_reg VPR[32];
u128 VPR[32];
u32 vpcr;
CRhdr CR; //Condition Register
@ -743,7 +690,7 @@ public:
for(uint i=0; i<32; ++i) ret += fmt::Format("GPR[%d] = 0x%llx\n", i, GPR[i]);
for(uint i=0; i<32; ++i) ret += fmt::Format("FPR[%d] = %.6G\n", i, (double)FPR[i]);
for(uint i=0; i<32; ++i) ret += fmt::Format("VPR[%d] = 0x%s [%s]\n", i, (const char*)VPR[i].ToString(true).c_str(), (const char*)VPR[i].ToString().c_str());
for(uint i=0; i<32; ++i) ret += fmt::Format("VPR[%d] = 0x%s [%s]\n", i, VPR[i].to_hex().c_str(), VPR[i].to_xyzw().c_str());
ret += fmt::Format("CR = 0x%08x\n", CR.CR);
ret += fmt::Format("LR = 0x%llx\n", LR);
ret += fmt::Format("CTR = 0x%llx\n", CTR);

210
rpcs3/Emu/Cell/SPUInterpreter.h
View file

@ -55,7 +55,7 @@ private:
}
void RCHCNT(u32 rt, u32 ra)
{
CPU.GPR[rt].Reset();
CPU.GPR[rt].clear();
CPU.GPR[rt]._u32[3] = CPU.GetChannelCount(ra);
}
void SF(u32 rt, u32 ra, u32 rb)
@ -112,10 +112,10 @@ private:
}
void ROTMA(u32 rt, u32 ra, u32 rb)
{
CPU.GPR[rt]._i32[0] = ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) < 32 ? CPU.GPR[ra]._i32[0] >> ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) : CPU.GPR[ra]._i32[0] >> 31;
CPU.GPR[rt]._i32[1] = ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) < 32 ? CPU.GPR[ra]._i32[1] >> ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) : CPU.GPR[ra]._i32[1] >> 31;
CPU.GPR[rt]._i32[2] = ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) < 32 ? CPU.GPR[ra]._i32[2] >> ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) : CPU.GPR[ra]._i32[2] >> 31;
CPU.GPR[rt]._i32[3] = ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) < 32 ? CPU.GPR[ra]._i32[3] >> ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) : CPU.GPR[ra]._i32[3] >> 31;
CPU.GPR[rt]._s32[0] = ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[0] >> ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) : CPU.GPR[ra]._s32[0] >> 31;
CPU.GPR[rt]._s32[1] = ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[1] >> ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) : CPU.GPR[ra]._s32[1] >> 31;
CPU.GPR[rt]._s32[2] = ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[2] >> ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) : CPU.GPR[ra]._s32[2] >> 31;
CPU.GPR[rt]._s32[3] = ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[3] >> ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) : CPU.GPR[ra]._s32[3] >> 31;
}
void SHL(u32 rt, u32 ra, u32 rb)
{
@ -137,7 +137,7 @@ private:
void ROTMAH(u32 rt, u32 ra, u32 rb)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._i16[h] = ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) < 16 ? CPU.GPR[ra]._i16[h] >> ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) : CPU.GPR[ra]._i16[h] >> 15;
CPU.GPR[rt]._s16[h] = ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) < 16 ? CPU.GPR[ra]._s16[h] >> ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) : CPU.GPR[ra]._s16[h] >> 15;
}
void SHLH(u32 rt, u32 ra, u32 rb)
{
@ -163,10 +163,10 @@ private:
void ROTMAI(u32 rt, u32 ra, s32 i7)
{
const int nRot = (0 - i7) & 0x3f;
CPU.GPR[rt]._i32[0] = nRot < 32 ? CPU.GPR[ra]._i32[0] >> nRot : CPU.GPR[ra]._i32[0] >> 31;
CPU.GPR[rt]._i32[1] = nRot < 32 ? CPU.GPR[ra]._i32[1] >> nRot : CPU.GPR[ra]._i32[1] >> 31;
CPU.GPR[rt]._i32[2] = nRot < 32 ? CPU.GPR[ra]._i32[2] >> nRot : CPU.GPR[ra]._i32[2] >> 31;
CPU.GPR[rt]._i32[3] = nRot < 32 ? CPU.GPR[ra]._i32[3] >> nRot : CPU.GPR[ra]._i32[3] >> 31;
CPU.GPR[rt]._s32[0] = nRot < 32 ? CPU.GPR[ra]._s32[0] >> nRot : CPU.GPR[ra]._s32[0] >> 31;
CPU.GPR[rt]._s32[1] = nRot < 32 ? CPU.GPR[ra]._s32[1] >> nRot : CPU.GPR[ra]._s32[1] >> 31;
CPU.GPR[rt]._s32[2] = nRot < 32 ? CPU.GPR[ra]._s32[2] >> nRot : CPU.GPR[ra]._s32[2] >> 31;
CPU.GPR[rt]._s32[3] = nRot < 32 ? CPU.GPR[ra]._s32[3] >> nRot : CPU.GPR[ra]._s32[3] >> 31;
}
void SHLI(u32 rt, u32 ra, s32 i7)
{
@ -194,7 +194,7 @@ private:
const int nRot = (0 - i7) & 0x1f;
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._i16[h] = nRot < 16 ? CPU.GPR[ra]._i16[h] >> nRot : CPU.GPR[ra]._i16[h] >> 15;
CPU.GPR[rt]._s16[h] = nRot < 16 ? CPU.GPR[ra]._s16[h] >> nRot : CPU.GPR[ra]._s16[h] >> 15;
}
void SHLHI(u32 rt, u32 ra, s32 i7)
{
@ -333,7 +333,7 @@ private:
{
u32 lsa = (CPU.GPR[ra]._u32[3] + CPU.GPR[rb]._u32[3]) & 0x3fff0;
CPU.WriteLS128(lsa, CPU.GPR[rt]._u128);
CPU.WriteLS128(lsa, CPU.GPR[rt]);
}
void BI(u32 intr, u32 ra)
{
@ -356,7 +356,7 @@ private:
}
u64 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
CPU.GPR[rt].Reset();
CPU.GPR[rt].clear();
CPU.GPR[rt]._u32[3] = (u32)CPU.PC + 4;
LOG5_OPCODE("branch (0x%llx)", target);
CPU.SetBranch(target);
@ -436,28 +436,28 @@ private:
u32 lsa = (a + b) & 0x3fff0;
CPU.GPR[rt]._u128 = CPU.ReadLS128(lsa);
CPU.GPR[rt] = CPU.ReadLS128(lsa);
}
void ROTQBYBI(u32 rt, u32 ra, u32 rb)
{
const int s = (CPU.GPR[rb]._u32[3] >> 3) & 0xf;
const SPU_GPR_hdr temp = CPU.GPR[ra];
const u128 temp = CPU.GPR[ra];
for (int b = 0; b < 16; b++)
CPU.GPR[rt]._u8[b] = temp._u8[(b - s) & 0xf];
}
void ROTQMBYBI(u32 rt, u32 ra, u32 rb)
{
const int s = (0 - (CPU.GPR[rb]._u32[3] >> 3)) & 0x1f;
const SPU_GPR_hdr temp = CPU.GPR[ra];
CPU.GPR[rt].Reset();
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt].clear();
for (int b = 0; b < 16 - s; b++)
CPU.GPR[rt]._u8[b] = temp._u8[b + s];
}
void SHLQBYBI(u32 rt, u32 ra, u32 rb)
{
const int s = (CPU.GPR[rb]._u32[3] >> 3) & 0x1f;
const SPU_GPR_hdr temp = CPU.GPR[ra];
CPU.GPR[rt].Reset();
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt].clear();
for (int b = s; b < 16; b++)
CPU.GPR[rt]._u8[b] = temp._u8[b - s];
}
@ -498,7 +498,7 @@ private:
const int t = CPU.GPR[rb]._u32[3] & 0x7;
if (t) // not an optimization, it fixes shifts
{
const SPU_GPR_hdr temp = CPU.GPR[ra];
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt]._u32[0] = (temp._u32[0] << t) | (temp._u32[3] >> (32 - t));
CPU.GPR[rt]._u32[1] = (temp._u32[1] << t) | (temp._u32[0] >> (32 - t));
CPU.GPR[rt]._u32[2] = (temp._u32[2] << t) | (temp._u32[1] >> (32 - t));
@ -514,7 +514,7 @@ private:
const int t = (0 - CPU.GPR[rb]._u32[3]) & 0x7;
if (t) // not an optimization, it fixes shifts
{
const SPU_GPR_hdr temp = CPU.GPR[ra];
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt]._u32[0] = (temp._u32[0] >> t) | (temp._u32[1] << (32 - t));
CPU.GPR[rt]._u32[1] = (temp._u32[1] >> t) | (temp._u32[2] << (32 - t));
CPU.GPR[rt]._u32[2] = (temp._u32[2] >> t) | (temp._u32[3] << (32 - t));
@ -530,7 +530,7 @@ private:
const int t = CPU.GPR[rb]._u32[3] & 0x7;
if (t) // not an optimization, it fixes shifts
{
const SPU_GPR_hdr temp = CPU.GPR[ra];
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt]._u32[0] = (temp._u32[0] << t);
CPU.GPR[rt]._u32[1] = (temp._u32[1] << t) | (temp._u32[0] >> (32 - t));
CPU.GPR[rt]._u32[2] = (temp._u32[2] << t) | (temp._u32[1] >> (32 - t));
@ -544,23 +544,23 @@ private:
void ROTQBY(u32 rt, u32 ra, u32 rb)
{
const int s = CPU.GPR[rb]._u32[3] & 0xf;
const SPU_GPR_hdr temp = CPU.GPR[ra];
const u128 temp = CPU.GPR[ra];
for (int b = 0; b < 16; ++b)
CPU.GPR[rt]._u8[b] = temp._u8[(b - s) & 0xf];
}
void ROTQMBY(u32 rt, u32 ra, u32 rb)
{
const int s = (0 - CPU.GPR[rb]._u32[3]) & 0x1f;
const SPU_GPR_hdr temp = CPU.GPR[ra];
CPU.GPR[rt].Reset();
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt].clear();
for (int b = 0; b < 16 - s; b++)
CPU.GPR[rt]._u8[b] = temp._u8[b + s];
}
void SHLQBY(u32 rt, u32 ra, u32 rb)
{
const int s = CPU.GPR[rb]._u32[3] & 0x1f;
const SPU_GPR_hdr temp = CPU.GPR[ra];
CPU.GPR[rt].Reset();
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt].clear();
for (int b = s; b < 16; b++)
CPU.GPR[rt]._u8[b] = temp._u8[b - s];
}
@ -607,7 +607,7 @@ private:
const int s = i7 & 0x7;
if (s) // not an optimization, it fixes shifts
{
const SPU_GPR_hdr temp = CPU.GPR[ra];
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt]._u32[0] = (temp._u32[0] << s) | (temp._u32[3] >> (32 - s));
CPU.GPR[rt]._u32[1] = (temp._u32[1] << s) | (temp._u32[0] >> (32 - s));
CPU.GPR[rt]._u32[2] = (temp._u32[2] << s) | (temp._u32[1] >> (32 - s));
@ -623,7 +623,7 @@ private:
const int s = (0 - i7) & 0x7;
if (s) // not an optimization, it fixes shifts
{
const SPU_GPR_hdr temp = CPU.GPR[ra];
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt]._u32[0] = (temp._u32[0] >> s) | (temp._u32[1] << (32 - s));
CPU.GPR[rt]._u32[1] = (temp._u32[1] >> s) | (temp._u32[2] << (32 - s));
CPU.GPR[rt]._u32[2] = (temp._u32[2] >> s) | (temp._u32[3] << (32 - s));
@ -639,7 +639,7 @@ private:
const int s = i7 & 0x7;
if (s) // not an optimization, it fixes shifts
{
const SPU_GPR_hdr temp = CPU.GPR[ra];
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt]._u32[0] = (temp._u32[0] << s);
CPU.GPR[rt]._u32[1] = (temp._u32[1] << s) | (temp._u32[0] >> (32 - s));
CPU.GPR[rt]._u32[2] = (temp._u32[2] << s) | (temp._u32[1] >> (32 - s));
@ -653,23 +653,23 @@ private:
void ROTQBYI(u32 rt, u32 ra, s32 i7)
{
const int s = i7 & 0xf;
const SPU_GPR_hdr temp = CPU.GPR[ra];
const u128 temp = CPU.GPR[ra];
for (int b = 0; b < 16; b++)
CPU.GPR[rt]._u8[b] = temp._u8[(b - s) & 0xf];
}
void ROTQMBYI(u32 rt, u32 ra, s32 i7)
{
const int s = (0 - i7) & 0x1f;
const SPU_GPR_hdr temp = CPU.GPR[ra];
CPU.GPR[rt].Reset();
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt].clear();
for (int b = 0; b < 16 - s; b++)
CPU.GPR[rt]._u8[b] = temp._u8[b + s];
}
void SHLQBYI(u32 rt, u32 ra, s32 i7)
{
const int s = i7 & 0x1f;
const SPU_GPR_hdr temp = CPU.GPR[ra];
CPU.GPR[rt].Reset();
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt].clear();
for (int b = s; b < 16; b++)
CPU.GPR[rt]._u8[b] = temp._u8[b - s];
}
@ -679,7 +679,7 @@ private:
void CGT(u32 rt, u32 ra, u32 rb)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._i32[w] > CPU.GPR[rb]._i32[w] ? 0xffffffff : 0;
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._s32[w] > CPU.GPR[rb]._s32[w] ? 0xffffffff : 0;
}
void XOR(u32 rt, u32 ra, u32 rb)
{
@ -689,7 +689,7 @@ private:
void CGTH(u32 rt, u32 ra, u32 rb)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._i16[h] > CPU.GPR[rb]._i16[h] ? 0xffff : 0;
CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._s16[h] > CPU.GPR[rb]._s16[h] ? 0xffff : 0;
}
void EQV(u32 rt, u32 ra, u32 rb)
{
@ -699,12 +699,12 @@ private:
void CGTB(u32 rt, u32 ra, u32 rb)
{
for (int b = 0; b < 16; b++)
CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._i8[b] > CPU.GPR[rb]._i8[b] ? 0xff : 0;
CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._s8[b] > CPU.GPR[rb]._s8[b] ? 0xff : 0;
}
void SUMB(u32 rt, u32 ra, u32 rb)
{
const SPU_GPR_hdr _a = CPU.GPR[ra];
const SPU_GPR_hdr _b = CPU.GPR[rb];
const u128 _a = CPU.GPR[ra];
const u128 _b = CPU.GPR[rb];
for (int w = 0; w < 4; w++)
{
CPU.GPR[rt]._u16[w*2] = _a._u8[w*4] + _a._u8[w*4 + 1] + _a._u8[w*4 + 2] + _a._u8[w*4 + 3];
@ -714,7 +714,7 @@ private:
//HGT uses signed values. HLGT uses unsigned values
void HGT(u32 rt, s32 ra, s32 rb)
{
if (CPU.GPR[ra]._i32[3] > CPU.GPR[rb]._i32[3])
if (CPU.GPR[ra]._s32[3] > CPU.GPR[rb]._s32[3])
{
CPU.SPU.Status.SetValue(SPU_STATUS_STOPPED_BY_HALT);
CPU.Stop();
@ -735,18 +735,18 @@ private:
}
void XSWD(u32 rt, u32 ra)
{
CPU.GPR[rt]._i64[0] = (s64)CPU.GPR[ra]._i32[0];
CPU.GPR[rt]._i64[1] = (s64)CPU.GPR[ra]._i32[2];
CPU.GPR[rt]._s64[0] = (s64)CPU.GPR[ra]._s32[0];
CPU.GPR[rt]._s64[1] = (s64)CPU.GPR[ra]._s32[2];
}
void XSHW(u32 rt, u32 ra)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = (s32)CPU.GPR[ra]._i16[w*2];
CPU.GPR[rt]._s32[w] = (s32)CPU.GPR[ra]._s16[w*2];
}
void CNTB(u32 rt, u32 ra)
{
const SPU_GPR_hdr temp = CPU.GPR[ra];
CPU.GPR[rt].Reset();
const u128 temp = CPU.GPR[ra];
CPU.GPR[rt].clear();
for (int b = 0; b < 16; b++)
for (int i = 0; i < 8; i++)
CPU.GPR[rt]._u8[b] += (temp._u8[b] & (1 << i)) ? 1 : 0;
@ -754,7 +754,7 @@ private:
void XSBH(u32 rt, u32 ra)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._i16[h] = (s16)CPU.GPR[ra]._i8[h*2];
CPU.GPR[rt]._s16[h] = (s16)CPU.GPR[ra]._s8[h*2];
}
void CLGT(u32 rt, u32 ra, u32 rb)
{
@ -875,7 +875,7 @@ private:
void CEQ(u32 rt, u32 ra, u32 rb)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._i32[w] == CPU.GPR[rb]._i32[w] ? 0xffffffff : 0;
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._s32[w] == CPU.GPR[rb]._s32[w] ? 0xffffffff : 0;
}
void MPYHHU(u32 rt, u32 ra, u32 rb)
{
@ -912,7 +912,7 @@ private:
void MPYHHA(u32 rt, u32 ra, u32 rb)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] += CPU.GPR[ra]._i16[w*2+1] * CPU.GPR[rb]._i16[w*2+1];
CPU.GPR[rt]._s32[w] += CPU.GPR[ra]._s16[w*2+1] * CPU.GPR[rb]._s16[w*2+1];
}
void MPYHHAU(u32 rt, u32 ra, u32 rb)
{
@ -924,7 +924,7 @@ private:
void FSCRRD(u32 rt)
{
// TODO (rarely used)
CPU.GPR[rt].Reset();
CPU.GPR[rt].clear();
}
void FESD(u32 rt, u32 ra)
{
@ -941,9 +941,9 @@ private:
void FSCRWR(u32 rt, u32 ra)
{
// TODO (rarely used)
if (CPU.GPR[ra]._u128)
if (CPU.GPR[ra]._u64[0] || CPU.GPR[ra]._u64[1])
{
LOG_ERROR(SPU, "FSCRWR(%d,%d): value = %s", rt, ra, CPU.GPR[ra].ToString().c_str());
LOG_ERROR(SPU, "FSCRWR(%d,%d): value = %s", rt, ra, CPU.GPR[ra].to_hex().c_str());
UNIMPLEMENTED();
}
}
@ -965,22 +965,22 @@ private:
void MPY(u32 rt, u32 ra, u32 rb)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2];
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2] * CPU.GPR[rb]._s16[w*2];
}
void MPYH(u32 rt, u32 ra, u32 rb)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = (CPU.GPR[ra]._i16[w*2+1] * CPU.GPR[rb]._i16[w*2]) << 16;
CPU.GPR[rt]._s32[w] = (CPU.GPR[ra]._s16[w*2+1] * CPU.GPR[rb]._s16[w*2]) << 16;
}
void MPYHH(u32 rt, u32 ra, u32 rb)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2+1] * CPU.GPR[rb]._i16[w*2+1];
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2+1] * CPU.GPR[rb]._s16[w*2+1];
}
void MPYS(u32 rt, u32 ra, u32 rb)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = (CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2]) >> 16;
CPU.GPR[rt]._s32[w] = (CPU.GPR[ra]._s16[w*2] * CPU.GPR[rb]._s16[w*2]) >> 16;
}
void CEQH(u32 rt, u32 ra, u32 rb)
{
@ -1016,7 +1016,7 @@ private:
}
void HEQ(u32 rt, u32 ra, u32 rb)
{
if (CPU.GPR[ra]._i32[3] == CPU.GPR[rb]._i32[3])
if (CPU.GPR[ra]._s32[3] == CPU.GPR[rb]._s32[3])
{
CPU.SPU.Status.SetValue(SPU_STATUS_STOPPED_BY_HALT);
CPU.Stop();
@ -1041,7 +1041,7 @@ private:
else if (CPU.GPR[rt]._f[i] < -pow(2, 31))
CPU.GPR[rt]._u32[i] = 0x80000000;
else
CPU.GPR[rt]._i32[i] = (s32)CPU.GPR[rt]._f[i]; //trunc
CPU.GPR[rt]._s32[i] = (s32)CPU.GPR[rt]._f[i]; //trunc
}
}
void CFLTU(u32 rt, u32 ra, s32 i8)
@ -1072,7 +1072,7 @@ private:
const u32 scale = 155 - (i8 & 0xff); //unsigned immediate
for (int i = 0; i < 4; i++)
{
CPU.GPR[rt]._f[i] = (float)CPU.GPR[ra]._i32[i];
CPU.GPR[rt]._f[i] = (float)CPU.GPR[ra]._s32[i];
u32 exp = ((CPU.GPR[rt]._u32[i] >> 23) & 0xff) - scale;
@ -1115,7 +1115,7 @@ private:
{
u32 lsa = (i16 << 2) & 0x3fff0;
CPU.WriteLS128(lsa, CPU.GPR[rt]._u128);
CPU.WriteLS128(lsa, CPU.GPR[rt]);
}
void BRNZ(u32 rt, s32 i16)
{
@ -1160,7 +1160,7 @@ private:
{
u32 lsa = branchTarget(CPU.PC, i16) & 0x3fff0;
CPU.WriteLS128(lsa, CPU.GPR[rt]._u128);
CPU.WriteLS128(lsa, CPU.GPR[rt]);
}
void BRA(s32 i16)
{
@ -1172,12 +1172,12 @@ private:
{
u32 lsa = (i16 << 2) & 0x3fff0;
CPU.GPR[rt]._u128 = CPU.ReadLS128(lsa);
CPU.GPR[rt] = CPU.ReadLS128(lsa);
}
void BRASL(u32 rt, s32 i16)
{
u64 target = branchTarget(0, i16);
CPU.GPR[rt].Reset();
CPU.GPR[rt].clear();
CPU.GPR[rt]._u32[3] = (u32)CPU.PC + 4;
LOG5_OPCODE("branch (0x%llx)", target);
CPU.SetBranch(target);
@ -1207,7 +1207,7 @@ private:
void BRSL(u32 rt, s32 i16)
{
u64 target = branchTarget(CPU.PC, i16);
CPU.GPR[rt].Reset();
CPU.GPR[rt].clear();
CPU.GPR[rt]._u32[3] = (u32)CPU.PC + 4;
LOG5_OPCODE("branch (0x%llx)", target);
CPU.SetBranch(target);
@ -1216,29 +1216,29 @@ private:
{
u32 lsa = branchTarget(CPU.PC, i16) & 0x3fff0;
CPU.GPR[rt]._u128 = CPU.ReadLS128(lsa);
CPU.GPR[rt] = CPU.ReadLS128(lsa);
}
void IL(u32 rt, s32 i16)
{
CPU.GPR[rt]._i32[0] =
CPU.GPR[rt]._i32[1] =
CPU.GPR[rt]._i32[2] =
CPU.GPR[rt]._i32[3] = i16;
CPU.GPR[rt]._s32[0] =
CPU.GPR[rt]._s32[1] =
CPU.GPR[rt]._s32[2] =
CPU.GPR[rt]._s32[3] = i16;
}
void ILHU(u32 rt, s32 i16)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = i16 << 16;
CPU.GPR[rt]._s32[w] = i16 << 16;
}
void ILH(u32 rt, s32 i16)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._i16[h] = i16;
CPU.GPR[rt]._s16[h] = i16;
}
void IOHL(u32 rt, s32 i16)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] |= (i16 & 0xFFFF);
CPU.GPR[rt]._s32[w] |= (i16 & 0xFFFF);
}
@ -1246,101 +1246,101 @@ private:
void ORI(u32 rt, u32 ra, s32 i10)
{
for(u32 i = 0; i < 4; ++i)
CPU.GPR[rt]._i32[i] = CPU.GPR[ra]._i32[i] | i10;
CPU.GPR[rt]._s32[i] = CPU.GPR[ra]._s32[i] | i10;
}
void ORHI(u32 rt, u32 ra, s32 i10)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._i16[h] = CPU.GPR[ra]._i16[h] | i10;
CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] | i10;
}
void ORBI(u32 rt, u32 ra, s32 i10)
{
for (int b = 0; b < 16; b++)
CPU.GPR[rt]._i8[b] = CPU.GPR[ra]._i8[b] | i10;
CPU.GPR[rt]._s8[b] = CPU.GPR[ra]._s8[b] | i10;
}
void SFI(u32 rt, u32 ra, s32 i10)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = i10 - CPU.GPR[ra]._i32[w];
CPU.GPR[rt]._s32[w] = i10 - CPU.GPR[ra]._s32[w];
}
void SFHI(u32 rt, u32 ra, s32 i10)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._i16[h] = i10 - CPU.GPR[ra]._i16[h];
CPU.GPR[rt]._s16[h] = i10 - CPU.GPR[ra]._s16[h];
}
void ANDI(u32 rt, u32 ra, s32 i10)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i32[w] & i10;
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s32[w] & i10;
}
void ANDHI(u32 rt, u32 ra, s32 i10)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._i16[h] = CPU.GPR[ra]._i16[h] & i10;
CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] & i10;
}
void ANDBI(u32 rt, u32 ra, s32 i10)
{
for (int b = 0; b < 16; b++)
CPU.GPR[rt]._i8[b] = CPU.GPR[ra]._i8[b] & i10;
CPU.GPR[rt]._s8[b] = CPU.GPR[ra]._s8[b] & i10;
}
void AI(u32 rt, u32 ra, s32 i10)
{
CPU.GPR[rt]._i32[0] = CPU.GPR[ra]._i32[0] + i10;
CPU.GPR[rt]._i32[1] = CPU.GPR[ra]._i32[1] + i10;
CPU.GPR[rt]._i32[2] = CPU.GPR[ra]._i32[2] + i10;
CPU.GPR[rt]._i32[3] = CPU.GPR[ra]._i32[3] + i10;
CPU.GPR[rt]._s32[0] = CPU.GPR[ra]._s32[0] + i10;
CPU.GPR[rt]._s32[1] = CPU.GPR[ra]._s32[1] + i10;
CPU.GPR[rt]._s32[2] = CPU.GPR[ra]._s32[2] + i10;
CPU.GPR[rt]._s32[3] = CPU.GPR[ra]._s32[3] + i10;
}
void AHI(u32 rt, u32 ra, s32 i10)
{
for(u32 h = 0; h < 8; ++h)
CPU.GPR[rt]._i16[h] = CPU.GPR[ra]._i16[h] + i10;
CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] + i10;
}
void STQD(u32 rt, s32 i10, u32 ra) //i10 is shifted left by 4 while decoding
{
const u32 lsa = (CPU.GPR[ra]._i32[3] + i10) & 0x3fff0;
const u32 lsa = (CPU.GPR[ra]._s32[3] + i10) & 0x3fff0;
//LOG_NOTICE(Log::SPU, "STQD(lsa=0x%x): GPR[%d] (0x%llx%llx)", lsa, rt, CPU.GPR[rt]._u64[1], CPU.GPR[rt]._u64[0]);
CPU.WriteLS128(lsa, CPU.GPR[rt]._u128);
CPU.WriteLS128(lsa, CPU.GPR[rt]);
}
void LQD(u32 rt, s32 i10, u32 ra) //i10 is shifted left by 4 while decoding
{
const u32 lsa = (CPU.GPR[ra]._i32[3] + i10) & 0x3fff0;
const u32 lsa = (CPU.GPR[ra]._s32[3] + i10) & 0x3fff0;
CPU.GPR[rt]._u128 = CPU.ReadLS128(lsa);
CPU.GPR[rt] = CPU.ReadLS128(lsa);
}
void XORI(u32 rt, u32 ra, s32 i10)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i32[w] ^ i10;
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s32[w] ^ i10;
}
void XORHI(u32 rt, u32 ra, s32 i10)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._i16[h] = CPU.GPR[ra]._i16[h] ^ i10;
CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] ^ i10;
}
void XORBI(u32 rt, u32 ra, s32 i10)
{
for (int b = 0; b < 16; b++)
CPU.GPR[rt]._i8[b] = CPU.GPR[ra]._i8[b] ^ i10;
CPU.GPR[rt]._s8[b] = CPU.GPR[ra]._s8[b] ^ i10;
}
void CGTI(u32 rt, u32 ra, s32 i10)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._i32[w] > i10 ? 0xffffffff : 0;
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._s32[w] > i10 ? 0xffffffff : 0;
}
void CGTHI(u32 rt, u32 ra, s32 i10)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._i16[h] > i10 ? 0xffff : 0;
CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._s16[h] > i10 ? 0xffff : 0;
}
void CGTBI(u32 rt, u32 ra, s32 i10)
{
for (int b = 0; b < 16; b++)
CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._i8[b] > (s8)(i10 & 0xff) ? 0xff : 0;
CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._s8[b] > (s8)(i10 & 0xff) ? 0xff : 0;
}
void HGTI(u32 rt, u32 ra, s32 i10)
{
if (CPU.GPR[ra]._i32[3] > i10)
if (CPU.GPR[ra]._s32[3] > i10)
{
CPU.SPU.Status.SetValue(SPU_STATUS_STOPPED_BY_HALT);
CPU.Stop();
@ -1376,7 +1376,7 @@ private:
void MPYI(u32 rt, u32 ra, s32 i10)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2] * i10;
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2] * i10;
}
void MPYUI(u32 rt, u32 ra, s32 i10)
{
@ -1386,21 +1386,21 @@ private:
void CEQI(u32 rt, u32 ra, s32 i10)
{
for(u32 i = 0; i < 4; ++i)
CPU.GPR[rt]._u32[i] = (CPU.GPR[ra]._i32[i] == i10) ? 0xffffffff : 0x00000000;
CPU.GPR[rt]._u32[i] = (CPU.GPR[ra]._s32[i] == i10) ? 0xffffffff : 0x00000000;
}
void CEQHI(u32 rt, u32 ra, s32 i10)
{
for (int h = 0; h < 8; h++)
CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._i16[h] == (s16)i10) ? 0xffff : 0;
CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._s16[h] == (s16)i10) ? 0xffff : 0;
}
void CEQBI(u32 rt, u32 ra, s32 i10)
{
for (int b = 0; b < 16; b++)
CPU.GPR[rt]._i8[b] = (CPU.GPR[ra]._i8[b] == (s8)(i10 & 0xff)) ? 0xff : 0;
CPU.GPR[rt]._s8[b] = (CPU.GPR[ra]._s8[b] == (s8)(i10 & 0xff)) ? 0xff : 0;
}
void HEQI(u32 rt, u32 ra, s32 i10)
{
if (CPU.GPR[ra]._i32[3] == i10)
if (CPU.GPR[ra]._s32[3] == i10)
{
CPU.SPU.Status.SetValue(SPU_STATUS_STOPPED_BY_HALT);
CPU.Stop();
@ -1435,8 +1435,8 @@ private:
}
void SHUFB(u32 rt, u32 ra, u32 rb, u32 rc)
{
const SPU_GPR_hdr _a = CPU.GPR[ra];
const SPU_GPR_hdr _b = CPU.GPR[rb];
const u128 _a = CPU.GPR[ra];
const u128 _b = CPU.GPR[rb];
for (int i = 0; i < 16; i++)
{
u8 b = CPU.GPR[rc]._u8[i];
@ -1464,7 +1464,7 @@ private:
void MPYA(u32 rt, u32 ra, u32 rb, u32 rc)
{
for (int w = 0; w < 4; w++)
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2] + CPU.GPR[rc]._i32[w];
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2] * CPU.GPR[rb]._s16[w*2] + CPU.GPR[rc]._s32[w];
}
void FNMS(u32 rt, u32 ra, u32 rb, u32 rc)
{
@ -1500,6 +1500,6 @@ private:
{
LOG_ERROR(Log::SPU, err + fmt::Format(" #pc: 0x%x", CPU.PC));
Emu.Pause();
for(uint i=0; i<128; ++i) LOG_NOTICE(Log::SPU, "r%d = 0x%s", i, CPU.GPR[i].ToString().c_str());
for(uint i=0; i<128; ++i) LOG_NOTICE(Log::SPU, "r%d = 0x%s", i, CPU.GPR[i].to_hex().c_str());
}
};

20
rpcs3/Emu/Cell/SPURecompiler.h
View file

@ -483,7 +483,7 @@ private:
{
c.mov(cpu_qword(PC), (u32)CPU.PC);
WRAPPER_BEGIN(rt, ra, yy, zz);
CPU.GPR[rt].Reset();
CPU.GPR[rt].clear();
CPU.GPR[rt]._u32[3] = CPU.GetChannelCount(ra);
WRAPPER_END(rt, ra, 0, 0);
// TODO
@ -1945,8 +1945,8 @@ private:
//HGT uses signed values. HLGT uses unsigned values
void HGT(u32 rt, s32 ra, s32 rb)
{
c.mov(*addr, cpu_dword(GPR[ra]._i32[3]));
c.cmp(*addr, cpu_dword(GPR[rb]._i32[3]));
c.mov(*addr, cpu_dword(GPR[ra]._s32[3]));
c.cmp(*addr, cpu_dword(GPR[rb]._s32[3]));
c.mov(*addr, 0);
c.setg(addr->r8());
c.neg(*addr);
@ -1970,10 +1970,10 @@ private:
}
void XSWD(u32 rt, u32 ra)
{
c.movsxd(*qw0, cpu_dword(GPR[ra]._i32[0]));
c.movsxd(*qw1, cpu_dword(GPR[ra]._i32[2]));
c.mov(cpu_qword(GPR[rt]._i64[0]), *qw0);
c.mov(cpu_qword(GPR[rt]._i64[1]), *qw1);
c.movsxd(*qw0, cpu_dword(GPR[ra]._s32[0]));
c.movsxd(*qw1, cpu_dword(GPR[ra]._s32[2]));
c.mov(cpu_qword(GPR[rt]._s64[0]), *qw0);
c.mov(cpu_qword(GPR[rt]._s64[1]), *qw1);
XmmInvalidate(rt);
LOG_OPCODE();
}
@ -2660,8 +2660,8 @@ private:
}
void HEQ(u32 rt, u32 ra, u32 rb)
{
c.mov(*addr, cpu_dword(GPR[ra]._i32[3]));
c.cmp(*addr, cpu_dword(GPR[rb]._i32[3]));
c.mov(*addr, cpu_dword(GPR[ra]._s32[3]));
c.cmp(*addr, cpu_dword(GPR[rb]._s32[3]));
c.mov(*addr, 0);
c.sete(addr->r8());
c.neg(*addr);
@ -3322,7 +3322,7 @@ private:
}
void HGTI(u32 rt, u32 ra, s32 i10)
{
c.mov(*addr, cpu_dword(GPR[ra]._i32[3]));
c.mov(*addr, cpu_dword(GPR[ra]._s32[3]));
c.cmp(*addr, i10);
c.mov(*addr, 0);
c.setg(addr->r8());

2
rpcs3/Emu/Cell/SPURecompilerCore.cpp
View file

@ -102,7 +102,7 @@ void SPURecompilerCore::Compile(u16 pos)
while (true)
{
const u32 opcode = Memory.Read32(CPU.dmac.ls_offset + pos * 4);
const u32 opcode = vm::read32(CPU.dmac.ls_offset + pos * 4);
m_enc->do_finalize = false;
if (opcode)
{

16
rpcs3/Emu/Cell/SPUThread.cpp
View file

@ -63,7 +63,7 @@ void SPUThread::DoReset()
PPCThread::DoReset();
//reset regs
memset(GPR, 0, sizeof(SPU_GPR_hdr) * 128);
memset(GPR, 0, sizeof(u128) * 128);
}
void SPUThread::InitRegs()
@ -198,7 +198,7 @@ void SPUThread::ProcessCmd(u32 cmd, u32 tag, u32 lsa, u64 ea, u32 size)
}
else if ((cmd & MFC_PUT_CMD) && size == 4 && (addr == SYS_SPU_THREAD_SNR1 || addr == SYS_SPU_THREAD_SNR2))
{
spu->WriteSNR(SYS_SPU_THREAD_SNR2 == addr, Memory.Read32(dmac.ls_offset + lsa));
spu->WriteSNR(SYS_SPU_THREAD_SNR2 == addr, vm::read32(dmac.ls_offset + lsa));
return;
}
else
@ -221,13 +221,13 @@ void SPUThread::ProcessCmd(u32 cmd, u32 tag, u32 lsa, u64 ea, u32 size)
{
case MFC_PUT_CMD:
{
Memory.Write32(ea, ReadLS32(lsa));
vm::write32(ea, ReadLS32(lsa));
return;
}
case MFC_GET_CMD:
{
WriteLS32(lsa, Memory.Read32(ea));
WriteLS32(lsa, vm::read32(ea));
return;
}
@ -450,7 +450,7 @@ void SPUThread::EnqMfcCmd(MFCReg& MFCArgs)
{
dis_asm.dump_pc = i;
dis_asm.offset = vm::get_ptr<u8>(dmac.ls_offset);
const u32 opcode = Memory.Read32(i + dmac.ls_offset);
const u32 opcode = vm::read32(i + dmac.ls_offset);
(*SPU_instr::rrr_list)(&dis_asm, opcode);
if (i >= 0 && i < 0x40000)
{
@ -533,7 +533,7 @@ u32 SPUThread::GetChannelCount(u32 ch)
}
}
void SPUThread::WriteChannel(u32 ch, const SPU_GPR_hdr& r)
void SPUThread::WriteChannel(u32 ch, const u128& r)
{
const u32 v = r._u32[3];
@ -861,9 +861,9 @@ void SPUThread::WriteChannel(u32 ch, const SPU_GPR_hdr& r)
if (Emu.IsStopped()) LOG_WARNING(Log::SPU, "%s(%s) aborted", __FUNCTION__, spu_ch_name[ch]);
}
void SPUThread::ReadChannel(SPU_GPR_hdr& r, u32 ch)
void SPUThread::ReadChannel(u128& r, u32 ch)
{
r.Reset();
r.clear();
u32& v = r._u32[3];
switch (ch)

59
rpcs3/Emu/Cell/SPUThread.h
View file

@ -191,37 +191,6 @@ public:
};
union SPU_GPR_hdr
{
u32 _u32[4];
float _f[4];
u128 _u128;
s128 _i128;
__m128 _m128;
__m128i _m128i;
u64 _u64[2];
s64 _i64[2];
s32 _i32[4];
u16 _u16[8];
s16 _i16[8];
u8 _u8[16];
s8 _i8[16];
double _d[2];
SPU_GPR_hdr() {}
std::string ToString() const
{
return fmt::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
}
void Reset()
{
memset(this, 0, sizeof(*this));
}
};
union SPU_SNRConfig_hdr
{
u64 value;
@ -244,7 +213,7 @@ struct SpuGroupInfo;
class SPUThread : public PPCThread
{
public:
SPU_GPR_hdr GPR[128]; // General-Purpose Registers
u128 GPR[128]; // General-Purpose Registers
//FPSCR FPSCR;
SPU_SNRConfig_hdr cfg; // Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2)
@ -516,23 +485,23 @@ public:
u32 GetChannelCount(u32 ch);
void WriteChannel(u32 ch, const SPU_GPR_hdr& r);
void WriteChannel(u32 ch, const u128& r);
void ReadChannel(SPU_GPR_hdr& r, u32 ch);
void ReadChannel(u128& r, u32 ch);
void StopAndSignal(u32 code);
u8 ReadLS8 (const u32 lsa) const { return Memory.Read8 (lsa + m_offset); }
u16 ReadLS16 (const u32 lsa) const { return Memory.Read16 (lsa + m_offset); }
u32 ReadLS32 (const u32 lsa) const { return Memory.Read32 (lsa + m_offset); }
u64 ReadLS64 (const u32 lsa) const { return Memory.Read64 (lsa + m_offset); }
u128 ReadLS128(const u32 lsa) const { return Memory.Read128(lsa + m_offset); }
u8 ReadLS8 (const u32 lsa) const { return vm::read8 (lsa + m_offset); }
u16 ReadLS16 (const u32 lsa) const { return vm::read16 (lsa + m_offset); }
u32 ReadLS32 (const u32 lsa) const { return vm::read32 (lsa + m_offset); }
u64 ReadLS64 (const u32 lsa) const { return vm::read64 (lsa + m_offset); }
u128 ReadLS128(const u32 lsa) const { return vm::read128(lsa + m_offset); }
void WriteLS8 (const u32 lsa, const u8& data) const { Memory.Write8 (lsa + m_offset, data); }
void WriteLS16 (const u32 lsa, const u16& data) const { Memory.Write16 (lsa + m_offset, data); }
void WriteLS32 (const u32 lsa, const u32& data) const { Memory.Write32 (lsa + m_offset, data); }
void WriteLS64 (const u32 lsa, const u64& data) const { Memory.Write64 (lsa + m_offset, data); }
void WriteLS128(const u32 lsa, const u128& data) const { Memory.Write128(lsa + m_offset, data); }
void WriteLS8 (const u32 lsa, const u8& data) const { vm::write8 (lsa + m_offset, data); }
void WriteLS16 (const u32 lsa, const u16& data) const { vm::write16 (lsa + m_offset, data); }
void WriteLS32 (const u32 lsa, const u32& data) const { vm::write32 (lsa + m_offset, data); }
void WriteLS64 (const u32 lsa, const u64& data) const { vm::write64 (lsa + m_offset, data); }
void WriteLS128(const u32 lsa, const u128& data) const { vm::write128(lsa + m_offset, data); }
public:
SPUThread(CPUThreadType type = CPU_THREAD_SPU);
@ -542,7 +511,7 @@ public:
{
std::string ret = "Registers:\n=========\n";
for(uint i=0; i<128; ++i) ret += fmt::Format("GPR[%d] = 0x%s\n", i, GPR[i].ToString().c_str());
for(uint i=0; i<128; ++i) ret += fmt::Format("GPR[%d] = 0x%s\n", i, GPR[i].to_hex().c_str());
return ret;
}

4
rpcs3/Emu/Memory/Memory.cpp
View file

@ -653,7 +653,7 @@ bool VirtualMemoryBlock::Read32(const u64 addr, u32* value)
u64 realAddr;
if (!getRealAddr(addr, realAddr))
return false;
*value = Memory.Read32(realAddr);
*value = vm::read32(realAddr);
return true;
}
@ -662,7 +662,7 @@ bool VirtualMemoryBlock::Write32(const u64 addr, const u32 value)
u64 realAddr;
if(!getRealAddr(addr, realAddr))
return false;
Memory.Write32(realAddr, value);
vm::write32(realAddr, value);
return true;
}

183
rpcs3/Emu/Memory/Memory.h
View file

@ -42,28 +42,13 @@ public:
MemoryBlock* RawSPUMem[(0x100000000 - RAW_SPU_BASE_ADDR) / RAW_SPU_OFFSET];
VirtualMemoryBlock RSXIOMem;
struct Wrapper32LE
{
void Write8(const u32 addr, const u8 data) { *(u8*)((u8*)m_base_addr + addr) = data; }
void Write16(const u32 addr, const u16 data) { *(u16*)((u8*)m_base_addr + addr) = data; }
void Write32(const u32 addr, const u32 data) { *(u32*)((u8*)m_base_addr + addr) = data; }
void Write64(const u32 addr, const u64 data) { *(u64*)((u8*)m_base_addr + addr) = data; }
void Write128(const u32 addr, const u128 data) { *(u128*)((u8*)m_base_addr + addr) = data; }
u8 Read8(const u32 addr) { return *(u8*)((u8*)m_base_addr + addr); }
u16 Read16(const u32 addr) { return *(u16*)((u8*)m_base_addr + addr); }
u32 Read32(const u32 addr) { return *(u32*)((u8*)m_base_addr + addr); }
u64 Read64(const u32 addr) { return *(u64*)((u8*)m_base_addr + addr); }
u128 Read128(const u32 addr) { return *(u128*)((u8*)m_base_addr + addr); }
};
struct : Wrapper32LE
struct
{
DynamicMemoryBlock RAM;
DynamicMemoryBlock Userspace;
} PSV;
struct : Wrapper32LE
struct
{
DynamicMemoryBlock Scratchpad;
DynamicMemoryBlock VRAM;
@ -116,29 +101,22 @@ public:
void Init(MemoryType type);
template<typename T> bool IsGoodAddr(const T addr)
bool IsGoodAddr(const u32 addr)
{
if ((u32)addr != addr || !m_pages[addr / 4096]) // TODO: define page parameters
{
return false;
}
else
{
return true;
}
return m_pages[addr / 4096] != 0; // TODO: define page parameters
}
template<typename T> bool IsGoodAddr(const T addr, const u32 size)
bool IsGoodAddr(const u32 addr, const u32 size)
{
if ((u32)addr != addr || (u64)addr + (u64)size > 0x100000000ull)
if (!size || addr + size - 1 < addr)
{
return false;
}
else
{
for (u32 i = (u32)addr / 4096; i <= ((u32)addr + size - 1) / 4096; i++)
for (u32 i = addr / 4096; i <= (addr + size - 1) / 4096; i++)
{
if (!m_pages[i]) return false; // TODO: define page parameters
if (m_pages[i] != 0) return false; // TODO: define page parameters
}
return true;
}
@ -146,155 +124,10 @@ public:
void Close();
//MemoryBase
template<typename T> void Write8(T addr, const u8 data)
{
if ((u32)addr == addr)
{
*(u8*)((u8*)GetBaseAddr() + addr) = data;
}
else
{
InvalidAddress(__FUNCTION__, addr);
*(u8*)GetBaseAddr() = data;
}
}
template<typename T> void Write16(T addr, const u16 data)
{
if ((u32)addr == addr)
{
*(u16*)((u8*)GetBaseAddr() + addr) = re16(data);
}
else
{
InvalidAddress(__FUNCTION__, addr);
*(u16*)GetBaseAddr() = data;
}
}
__noinline void WriteMMIO32(u32 addr, const u32 data);
template<typename T> void Write32(T addr, const u32 data)
{
if ((u32)addr == addr)
{
if (addr < RAW_SPU_BASE_ADDR || (addr % RAW_SPU_OFFSET) < RAW_SPU_PROB_OFFSET)
{
*(u32*)((u8*)GetBaseAddr() + addr) = re32(data);
}
else
{
WriteMMIO32((u32)addr, data);
}
}
else
{
InvalidAddress(__FUNCTION__, addr);
*(u32*)GetBaseAddr() = data;
}
}
template<typename T> void Write64(T addr, const u64 data)
{
if ((u32)addr == addr)
{
*(u64*)((u8*)GetBaseAddr() + addr) = re64(data);
}
else
{
InvalidAddress(__FUNCTION__, addr);
*(u64*)GetBaseAddr() = data;
}
}
template<typename T> void Write128(T addr, const u128 data)
{
if ((u32)addr == addr)
{
*(u128*)((u8*)GetBaseAddr() + addr) = re128(data);
}
else
{
InvalidAddress(__FUNCTION__, addr);
*(u128*)GetBaseAddr() = data;
}
}
template<typename T> u8 Read8(T addr)
{
if ((u32)addr == addr)
{
return *(u8*)((u8*)GetBaseAddr() + addr);
}
else
{
InvalidAddress(__FUNCTION__, addr);
return *(u8*)GetBaseAddr();
}
}
template<typename T> u16 Read16(T addr)
{
if ((u32)addr == addr)
{
return re16(*(u16*)((u8*)GetBaseAddr() + addr));
}
else
{
InvalidAddress(__FUNCTION__, addr);
return *(u16*)GetBaseAddr();
}
}
__noinline u32 ReadMMIO32(u32 addr);
template<typename T> u32 Read32(T addr)
{
if ((u32)addr == addr)
{
if (addr < RAW_SPU_BASE_ADDR || (addr % RAW_SPU_OFFSET) < RAW_SPU_PROB_OFFSET)
{
return re32(*(u32*)((u8*)GetBaseAddr() + addr));
}
else
{
return ReadMMIO32((u32)addr);
}
}
else
{
InvalidAddress(__FUNCTION__, addr);
return *(u32*)GetBaseAddr();
}
}
template<typename T> u64 Read64(T addr)
{
if ((u32)addr == addr)
{
return re64(*(u64*)((u8*)GetBaseAddr() + addr));
}
else
{
InvalidAddress(__FUNCTION__, addr);
return *(u64*)GetBaseAddr();
}
}
template<typename T> u128 Read128(T addr)
{
if ((u32)addr == addr)
{
return re128(*(u128*)((u8*)GetBaseAddr() + addr));
}
else
{
InvalidAddress(__FUNCTION__, addr);
return *(u128*)GetBaseAddr();
}
}
u32 GetUserMemTotalSize()
{
return UserMemory->GetSize();

14
rpcs3/Emu/RSX/RSXThread.cpp
View file

@ -262,7 +262,7 @@ void RSXThread::DoCmd(const u32 fcmd, const u32 cmd, const u32 args_addr, const
if(m_set_semaphore_offset)
{
m_set_semaphore_offset = false;
Memory.Write32(Memory.RSXCMDMem.GetStartAddr() + m_semaphore_offset, ARGS(0));
vm::write32(Memory.RSXCMDMem.GetStartAddr() + m_semaphore_offset, ARGS(0));
}
}
break;
@ -275,7 +275,7 @@ void RSXThread::DoCmd(const u32 fcmd, const u32 cmd, const u32 args_addr, const
u32 value = ARGS(0);
value = (value & 0xff00ff00) | ((value & 0xff) << 16) | ((value >> 16) & 0xff);
Memory.Write32(Memory.RSXCMDMem.GetStartAddr() + m_semaphore_offset, value);
vm::write32(Memory.RSXCMDMem.GetStartAddr() + m_semaphore_offset, value);
}
}
break;
@ -883,7 +883,7 @@ void RSXThread::DoCmd(const u32 fcmd, const u32 cmd, const u32 args_addr, const
{
int pos = (int)m_indexed_array.m_data.size();
m_indexed_array.m_data.resize(m_indexed_array.m_data.size() + 4);
index = Memory.Read32(m_indexed_array.m_addr + i * 4);
index = vm::read32(m_indexed_array.m_addr + i * 4);
*(u32*)&m_indexed_array.m_data[pos] = index;
//LOG_WARNING(RSX, "index 4: %d", *(u32*)&m_indexed_array.m_data[pos]);
}
@ -893,7 +893,7 @@ void RSXThread::DoCmd(const u32 fcmd, const u32 cmd, const u32 args_addr, const
{
int pos = (int)m_indexed_array.m_data.size();
m_indexed_array.m_data.resize(m_indexed_array.m_data.size() + 2);
index = Memory.Read16(m_indexed_array.m_addr + i * 2);
index = vm::read16(m_indexed_array.m_addr + i * 2);
//LOG_WARNING(RSX, "index 2: %d", index);
*(u16*)&m_indexed_array.m_data[pos] = index;
}
@ -1648,9 +1648,9 @@ void RSXThread::DoCmd(const u32 fcmd, const u32 cmd, const u32 args_addr, const
u64 timestamp = get_system_time() * 1000;
// TODO: Reports can be written to the main memory or the local memory (controlled by NV4097_SET_CONTEXT_DMA_REPORT)
Memory.Write64(m_local_mem_addr + offset + 0x0, timestamp);
Memory.Write32(m_local_mem_addr + offset + 0x8, value);
Memory.Write32(m_local_mem_addr + offset + 0xc, 0);
vm::write64(m_local_mem_addr + offset + 0x0, timestamp);
vm::write32(m_local_mem_addr + offset + 0x8, value);
vm::write32(m_local_mem_addr + offset + 0xc, 0);
}
break;

38
rpcs3/Emu/SysCalls/Modules.cpp
View file

@ -191,12 +191,12 @@ void Module::PushNewFuncSub(SFunc* func)
void fix_import(Module* module, u32 func, u32 addr)
{
Memory.Write32(addr + 0x0, 0x3d600000 | (func >> 16)); /* lis r11, (func_id >> 16) */
Memory.Write32(addr + 0x4, 0x616b0000 | (func & 0xffff)); /* ori r11, (func_id & 0xffff) */
Memory.Write32(addr + 0x8, 0x60000000); /* nop */
vm::write32(addr + 0x0, 0x3d600000 | (func >> 16)); /* lis r11, (func_id >> 16) */
vm::write32(addr + 0x4, 0x616b0000 | (func & 0xffff)); /* ori r11, (func_id & 0xffff) */
vm::write32(addr + 0x8, 0x60000000); /* nop */
// leave rtoc saving at 0xC
Memory.Write64(addr + 0x10, 0x440000024e800020ull); /* sc + blr */
Memory.Write64(addr + 0x18, 0x6000000060000000ull); /* nop + nop */
vm::write64(addr + 0x10, 0x440000024e800020ull); /* sc + blr */
vm::write64(addr + 0x18, 0x6000000060000000ull); /* nop + nop */
module->Load(func);
}
@ -211,36 +211,36 @@ void fix_relocs(Module* module, u32 lib, u32 start, u32 end, u32 seg2)
for (u32 i = lib + start; i < lib + end; i += 24)
{
u64 addr = Memory.Read64(i);
const u64 flag = Memory.Read64(i + 8);
u64 addr = vm::read64(i);
const u64 flag = vm::read64(i + 8);
if (flag == 0x10100000001ull)
{
addr = addr + seg2 + lib;
u32 value = Memory.Read32(addr);
assert(value == Memory.Read64(i + 16) + seg2);
Memory.Write32(addr, value + lib);
u32 value = vm::read32(addr);
assert(value == vm::read64(i + 16) + seg2);
vm::write32(addr, value + lib);
}
else if (flag == 0x100000001ull)
{
addr = addr + seg2 + lib;
u32 value = Memory.Read32(addr);
assert(value == Memory.Read64(i + 16));
Memory.Write32(addr, value + lib);
u32 value = vm::read32(addr);
assert(value == vm::read64(i + 16));
vm::write32(addr, value + lib);
}
else if (flag == 0x10000000001ull)
{
addr = addr + lib;
u32 value = Memory.Read32(addr);
assert(value == Memory.Read64(i + 16) + seg2);
Memory.Write32(addr, value + lib);
u32 value = vm::read32(addr);
assert(value == vm::read64(i + 16) + seg2);
vm::write32(addr, value + lib);
}
else if (flag == 1)
{
addr = addr + lib;
u32 value = Memory.Read32(addr);
assert(value == Memory.Read64(i + 16));
Memory.Write32(addr, value + lib);
u32 value = vm::read32(addr);
assert(value == vm::read64(i + 16));
vm::write32(addr, value + lib);
}
else if (flag == 0x10000000004ull || flag == 0x10000000006ull)
{

2
rpcs3/Emu/SysCalls/Modules/cellFont.cpp
View file

@ -555,7 +555,7 @@ int cellFontExtend(u32 a1, u32 a2, u32 a3)
{
//Something happens
}
if (Memory.Read32(a3) == 0)
if (vm::read32(a3) == 0)
{
//Something happens
}

2
rpcs3/Emu/SysCalls/Modules/cellFontFT.cpp
View file

@ -21,7 +21,7 @@ int cellFontInitLibraryFreeTypeWithRevision(u64 revisionFlags, vm::ptr<CellFontL
//if (s_fontInternalInstance->m_bInitialized)
//return CELL_FONT_ERROR_UNINITIALIZED;
Memory.Write32(lib_addr_addr, (u32)Memory.Alloc(sizeof(CellFontLibrary), 1));
vm::write32(lib_addr_addr, (u32)Memory.Alloc(sizeof(CellFontLibrary), 1));
return CELL_OK;
}

48
rpcs3/Emu/SysCalls/Modules/cellGcmSys.cpp
View file

@ -115,7 +115,7 @@ u64 cellGcmGetTimeStamp(u32 index)
cellGcmSys->Error("cellGcmGetTimeStamp: Wrong local index (%d)", index);
return 0;
}
return Memory.Read64(Memory.RSXFBMem.GetStartAddr() + index * 0x10);
return vm::read64(Memory.RSXFBMem.GetStartAddr() + index * 0x10);
}
int cellGcmGetCurrentField()
@ -133,7 +133,7 @@ u32 cellGcmGetNotifyDataAddress(u32 index)
cellGcmGetOffsetTable(table);
// If entry not in use, return NULL
u16 entry = Memory.Read16(table->eaAddress + 241 * sizeof(u16));
u16 entry = vm::read16(table->eaAddress + 241 * sizeof(u16));
if (entry == 0xFFFF) {
return 0;
}
@ -194,7 +194,7 @@ u64 cellGcmGetTimeStampLocation(u32 index, u32 location)
cellGcmSys->Error("cellGcmGetTimeStampLocation: Wrong local index (%d)", index);
return 0;
}
return Memory.Read64(Memory.RSXFBMem.GetStartAddr() + index * 0x10);
return vm::read64(Memory.RSXFBMem.GetStartAddr() + index * 0x10);
}
if (location == CELL_GCM_LOCATION_MAIN) {
@ -203,7 +203,7 @@ u64 cellGcmGetTimeStampLocation(u32 index, u32 location)
return 0;
}
// TODO: It seems m_report_main_addr is not initialized
return Memory.Read64(Emu.GetGSManager().GetRender().m_report_main_addr + index * 0x10);
return vm::read64(Emu.GetGSManager().GetRender().m_report_main_addr + index * 0x10);
}
cellGcmSys->Error("cellGcmGetTimeStampLocation: Wrong location (%d)", location);
@ -378,7 +378,7 @@ s32 _cellGcmInitBody(vm::ptr<CellGcmContextData> context, u32 cmdSize, u32 ioSiz
gcm_info.control_addr = gcm_info.context_addr + 0x40;
vm::get_ref<CellGcmContextData>(gcm_info.context_addr) = current_context;
Memory.Write32(context.addr(), gcm_info.context_addr);
vm::write32(context.addr(), gcm_info.context_addr);
auto& ctrl = vm::get_ref<CellGcmControl>(gcm_info.control_addr);
ctrl.put = 0;
@ -524,8 +524,8 @@ s32 cellGcmSetPrepareFlip(vm::ptr<CellGcmContextData> ctxt, u32 id)
}
current = ctxt->current;
Memory.Write32(current, 0x3fead | (1 << 18));
Memory.Write32(current + 4, id);
vm::write32(current, 0x3fead | (1 << 18));
vm::write32(current + 4, id);
ctxt->current += 8;
if(ctxt.addr() == gcm_info.context_addr)
@ -700,7 +700,7 @@ int cellGcmGetCurrentDisplayBufferId(u32 id_addr)
{
cellGcmSys->Warning("cellGcmGetCurrentDisplayBufferId(id_addr=0x%x)", id_addr);
Memory.Write32(id_addr, Emu.GetGSManager().GetRender().m_gcm_current_buffer);
vm::write32(id_addr, Emu.GetGSManager().GetRender().m_gcm_current_buffer);
return CELL_OK;
}
@ -818,7 +818,7 @@ s32 cellGcmAddressToOffset(u64 address, vm::ptr<be_t<u32>> offset)
// Address in main memory else check
else
{
u16 upper12Bits = Memory.Read16(offsetTable.ioAddress + sizeof(u16)*(address >> 20));
u16 upper12Bits = vm::read16(offsetTable.ioAddress + sizeof(u16)*(address >> 20));
// If the address is mapped in IO
if (upper12Bits != 0xFFFF) {
@ -857,7 +857,7 @@ s32 cellGcmIoOffsetToAddress(u32 ioOffset, u64 address)
if (!Memory.RSXIOMem.getRealAddr(Memory.RSXIOMem.GetStartAddr() + ioOffset, realAddr))
return CELL_GCM_ERROR_FAILURE;
Memory.Write64(address, realAddr);
vm::write64(address, realAddr);
return CELL_OK;
}
@ -874,8 +874,8 @@ s32 cellGcmMapEaIoAddress(u32 ea, u32 io, u32 size)
// Fill the offset table
for (u32 i = 0; i<(size >> 20); i++)
{
Memory.Write16(offsetTable.ioAddress + ((ea >> 20) + i)*sizeof(u16), (io >> 20) + i);
Memory.Write16(offsetTable.eaAddress + ((io >> 20) + i)*sizeof(u16), (ea >> 20) + i);
vm::write16(offsetTable.ioAddress + ((ea >> 20) + i)*sizeof(u16), (io >> 20) + i);
vm::write16(offsetTable.eaAddress + ((io >> 20) + i)*sizeof(u16), (ea >> 20) + i);
}
}
else
@ -902,8 +902,8 @@ s32 cellGcmMapLocalMemory(u64 address, u64 size)
local_size = 0xf900000; //TODO
local_addr = (u32)Memory.RSXFBMem.GetStartAddr();
Memory.RSXFBMem.AllocAlign(local_size);
Memory.Write32(address, local_addr);
Memory.Write32(size, local_size);
vm::write32(address, local_addr);
vm::write32(size, local_size);
}
else
{
@ -931,8 +931,8 @@ s32 cellGcmMapMainMemory(u32 ea, u32 size, vm::ptr<be_t<u32>> offset)
//fill the offset table
for (u32 i = 0; i<(size >> 20); i++)
{
Memory.Write16(offsetTable.ioAddress + ((ea >> 20) + i) * sizeof(u16), (u16)(io >> 20) + i);
Memory.Write16(offsetTable.eaAddress + ((io >> 20) + i) * sizeof(u16), (u16)(ea >> 20) + i);
vm::write16(offsetTable.ioAddress + ((ea >> 20) + i) * sizeof(u16), (u16)(io >> 20) + i);
vm::write16(offsetTable.eaAddress + ((io >> 20) + i) * sizeof(u16), (u16)(ea >> 20) + i);
}
*offset = io;
@ -977,12 +977,12 @@ s32 cellGcmUnmapEaIoAddress(u64 ea)
{
u64 io;
ea = ea >> 20;
io = Memory.Read16(offsetTable.ioAddress + (ea*sizeof(u16)));
io = vm::read16(offsetTable.ioAddress + (ea*sizeof(u16)));
for (u32 i = 0; i<size; i++)
{
Memory.Write16(offsetTable.ioAddress + ((ea + i)*sizeof(u16)), 0xFFFF);
Memory.Write16(offsetTable.eaAddress + ((io + i)*sizeof(u16)), 0xFFFF);
vm::write16(offsetTable.ioAddress + ((ea + i)*sizeof(u16)), 0xFFFF);
vm::write16(offsetTable.eaAddress + ((io + i)*sizeof(u16)), 0xFFFF);
}
}
else
@ -1003,12 +1003,12 @@ s32 cellGcmUnmapIoAddress(u64 io)
{
u64 ea;
io = io >> 20;
ea = Memory.Read16(offsetTable.eaAddress + (io*sizeof(u16)));
ea = vm::read16(offsetTable.eaAddress + (io*sizeof(u16)));
for (u32 i = 0; i<size; i++)
{
Memory.Write16(offsetTable.ioAddress + ((ea + i)*sizeof(u16)), 0xFFFF);
Memory.Write16(offsetTable.eaAddress + ((io + i)*sizeof(u16)), 0xFFFF);
vm::write16(offsetTable.ioAddress + ((ea + i)*sizeof(u16)), 0xFFFF);
vm::write16(offsetTable.eaAddress + ((io + i)*sizeof(u16)), 0xFFFF);
}
}
else
@ -1087,7 +1087,7 @@ int cellGcmSetCursorImageOffset(u32 offset)
void cellGcmSetDefaultCommandBuffer()
{
cellGcmSys->Warning("cellGcmSetDefaultCommandBuffer()");
Memory.Write32(Emu.GetGSManager().GetRender().m_ctxt_addr, gcm_info.context_addr);
vm::write32(Emu.GetGSManager().GetRender().m_ctxt_addr, gcm_info.context_addr);
}
//------------------------------------------------------------------------
@ -1107,7 +1107,7 @@ int cellGcmSetFlipCommandWithWaitLabel(vm::ptr<CellGcmContextData> ctx, u32 id,
ctx.addr(), id, label_index, label_value);
int res = cellGcmSetPrepareFlip(ctx, id);
Memory.Write32(Memory.RSXCMDMem.GetStartAddr() + 0x10 * label_index, label_value);
vm::write32(Memory.RSXCMDMem.GetStartAddr() + 0x10 * label_index, label_value);
return res < 0 ? CELL_GCM_ERROR_FAILURE : CELL_OK;
}

2
rpcs3/Emu/SysCalls/Modules/cellSync.cpp
View file

@ -1025,7 +1025,7 @@ void syncLFQueueDump(vm::ptr<CellSyncLFQueue> queue)
cellSync->Notice("CellSyncLFQueue dump: addr = 0x%x", queue.addr());
for (u32 i = 0; i < sizeof(CellSyncLFQueue) / 16; i++)
{
cellSync->Notice("*** 0x%.16llx 0x%.16llx", Memory.Read64(queue.addr() + i * 16), Memory.Read64(queue.addr() + i * 16 + 8));
cellSync->Notice("*** 0x%.16llx 0x%.16llx", vm::read64(queue.addr() + i * 16), vm::read64(queue.addr() + i * 16 + 8));
}
}

2
rpcs3/Emu/SysCalls/Modules/libmixer.cpp
View file

@ -547,7 +547,7 @@ int cellSurMixerSurBusAddData(u32 busNo, u32 offset, u32 addr, u32 samples)
for (u32 i = 0; i < samples; i++)
{
// reverse byte order and mix
u32 v = Memory.Read32(addr + i * sizeof(float));
u32 v = vm::read32(addr + i * sizeof(float));
mixdata[i*8+busNo] += (float&)v;
}

2
rpcs3/Emu/SysCalls/Modules/sceNp.cpp
View file

@ -40,7 +40,7 @@ int npDrmIsAvailable(u32 k_licensee_addr, vm::ptr<const char> drm_path)
{
for (int i = 0; i < 0x10; i++)
{
k_licensee[i] = Memory.Read8(k_licensee_addr + i);
k_licensee[i] = vm::read8(k_licensee_addr + i);
k_licensee_str += fmt::Format("%02x", k_licensee[i]);
}
}

12
rpcs3/Emu/SysCalls/Modules/sysPrxForUser.cpp
View file

@ -74,7 +74,7 @@ int sys_process_is_stack(u32 p)
sysPrxForUser->Log("sys_process_is_stack(p=0x%x)", p);
// prx: compare high 4 bits with "0xD"
return (int)(bool)(p >= Memory.StackMem.GetStartAddr() && p <= Memory.StackMem.GetEndAddr());
return (p >= Memory.StackMem.GetStartAddr() && p <= Memory.StackMem.GetEndAddr()) ? 1 : 0;
}
s64 sys_prx_exitspawn_with_level()
@ -144,7 +144,7 @@ int sys_raw_spu_image_load(int id, vm::ptr<sys_spu_image> img)
// TODO: use segment info
memcpy(vm::get_ptr<void>(RAW_SPU_BASE_ADDR + RAW_SPU_OFFSET * id), vm::get_ptr<void>(img->segs_addr), 256 * 1024);
Memory.Write32(RAW_SPU_BASE_ADDR + RAW_SPU_OFFSET * id + RAW_SPU_PROB_OFFSET + SPU_NPC_offs, (u32)img->entry_point);
vm::write32(RAW_SPU_BASE_ADDR + RAW_SPU_OFFSET * id + RAW_SPU_PROB_OFFSET + SPU_NPC_offs, (u32)img->entry_point);
return CELL_OK;
}
@ -260,7 +260,7 @@ s64 _sys_spu_printf_attach_group(u32 arg)
return CELL_ESTAT;
}
return GetCurrentPPUThread().FastCall(Memory.Read32(spu_printf_agcb), Memory.Read32(spu_printf_agcb + 4), arg);
return GetCurrentPPUThread().FastCall(vm::read32(spu_printf_agcb), vm::read32(spu_printf_agcb + 4), arg);
}
s64 _sys_spu_printf_detach_group(u32 arg)
@ -272,7 +272,7 @@ s64 _sys_spu_printf_detach_group(u32 arg)
return CELL_ESTAT;
}
return GetCurrentPPUThread().FastCall(Memory.Read32(spu_printf_dgcb), Memory.Read32(spu_printf_dgcb + 4), arg);
return GetCurrentPPUThread().FastCall(vm::read32(spu_printf_dgcb), vm::read32(spu_printf_dgcb + 4), arg);
}
s64 _sys_spu_printf_attach_thread(u32 arg)
@ -284,7 +284,7 @@ s64 _sys_spu_printf_attach_thread(u32 arg)
return CELL_ESTAT;
}
return GetCurrentPPUThread().FastCall(Memory.Read32(spu_printf_atcb), Memory.Read32(spu_printf_atcb + 4), arg);
return GetCurrentPPUThread().FastCall(vm::read32(spu_printf_atcb), vm::read32(spu_printf_atcb + 4), arg);
}
s64 _sys_spu_printf_detach_thread(u32 arg)
@ -296,7 +296,7 @@ s64 _sys_spu_printf_detach_thread(u32 arg)
return CELL_ESTAT;
}
return GetCurrentPPUThread().FastCall(Memory.Read32(spu_printf_dtcb), Memory.Read32(spu_printf_dtcb + 4), arg);
return GetCurrentPPUThread().FastCall(vm::read32(spu_printf_dtcb), vm::read32(spu_printf_dtcb + 4), arg);
}
s32 _sys_printf(vm::ptr<const char> fmt)

24
rpcs3/Emu/SysCalls/SC_FUNC.h
View file

@ -46,11 +46,11 @@ namespace detail
template<typename T, int g_count, int f_count, int v_count>
struct bind_arg<T, ARG_VECTOR, g_count, f_count, v_count>
{
static_assert(sizeof(T) == 16, "Wrong argument type for ARG_VECTOR");
static_assert(std::is_same<T, u128>::value, "Wrong argument type for ARG_VECTOR");
static __forceinline T func(PPUThread& CPU)
{
return (T&)CPU.VPR[v_count + 1]._u128;
return (T&)CPU.VPR[v_count + 1];
}
};
@ -69,9 +69,11 @@ namespace detail
template<typename T>
struct bind_result
{
static_assert(!std::is_pointer<T>::value, "Invalid function result type: pointer");
static_assert(sizeof(T) <= 8, "Invalid function result type");
static __forceinline void func(PPUThread& CPU, T value)
{
static_assert(!std::is_pointer<T>::value, "Invalid function result type: pointer");
if (std::is_floating_point<T>::value)
{
CPU.FPR[1] = (double)value;
@ -83,6 +85,15 @@ namespace detail
}
};
template<>
struct bind_result<u128>
{
static __forceinline void func(PPUThread& CPU, u128 value)
{
CPU.VPR[2] = value;
}
};
template <typename RT, typename F, typename Tuple, bool Done, int Total, int... N>
struct call_impl
{
@ -120,12 +131,13 @@ namespace detail
static_assert(!std::is_pointer<T>::value, "Invalid function argument type: pointer");
// TODO: check calculations
const bool is_float = std::is_floating_point<T>::value;
const bool is_vector = std::is_same<T, u128>::value;
const bind_arg_type t = is_float
? ((f_count >= 12) ? ARG_STACK : ARG_FLOAT)
: ((g_count >= 8) ? ARG_STACK : ARG_GENERAL);
const int g = g_count + (is_float ? 0 : 1);
: (is_vector ? ((v_count >= 12) ? ARG_STACK : ARG_VECTOR) : ((g_count >= 8) ? ARG_STACK : ARG_GENERAL));
const int g = g_count + (is_float || is_vector ? 0 : 1);
const int f = f_count + (is_float ? 1 : 0);
const int v = v_count; // TODO: vector argument support (if possible)
const int v = v_count + (is_vector ? 1 : 0);
return std::tuple_cat(std::tuple<T>(bind_arg<T, t, g, f, v>::func(CPU)), iterate<g, f, v, A...>(CPU));
}

4
rpcs3/Emu/SysCalls/lv2/sys_memory.cpp
View file

@ -33,7 +33,7 @@ s32 sys_memory_allocate(u32 size, u32 flags, u32 alloc_addr_addr)
// Write back the start address of the allocated area.
sys_memory.Log("Memory allocated! [addr: 0x%x, size: 0x%x]", addr, size);
Memory.Write32(alloc_addr_addr, addr);
vm::write32(alloc_addr_addr, addr);
return CELL_OK;
}
@ -70,7 +70,7 @@ s32 sys_memory_allocate_from_container(u32 size, u32 cid, u32 flags, u32 alloc_a
// Write back the start address of the allocated area.
sys_memory.Log("Memory allocated! [addr: 0x%x, size: 0x%x]", ct->addr, ct->size);
Memory.Write32(alloc_addr_addr, ct->addr);
vm::write32(alloc_addr_addr, ct->addr);
return CELL_OK;
}

6
rpcs3/Emu/SysCalls/lv2/sys_mmapper.cpp
View file

@ -37,7 +37,7 @@ s32 sys_mmapper_allocate_address(u32 size, u64 flags, u32 alignment, u32 alloc_a
}
// Write back the start address of the allocated area.
Memory.Write32(alloc_addr, addr);
vm::write32(alloc_addr, addr);
return CELL_OK;
}
@ -195,7 +195,7 @@ s32 sys_mmapper_search_and_map(u32 start_addr, u32 mem_id, u64 flags, u32 alloc_
return CELL_ENOMEM;
// Write back the start address of the allocated area.
Memory.Write32(alloc_addr, addr);
vm::write32(alloc_addr, addr);
// Keep track of mapped addresses.
mmapper_info_map[mem_id] = addr;
@ -209,7 +209,7 @@ s32 sys_mmapper_unmap_memory(u32 start_addr, u32 mem_id_addr)
// Write back the mem ID of the unmapped area.
u32 mem_id = mmapper_info_map.find(start_addr)->first;
Memory.Write32(mem_id_addr, mem_id);
vm::write32(mem_id_addr, mem_id);
return CELL_OK;
}

10
rpcs3/Emu/SysCalls/lv2/sys_ppu_thread.cpp
View file

@ -86,7 +86,7 @@ s32 sys_ppu_thread_detach(u64 thread_id)
void sys_ppu_thread_get_join_state(u32 isjoinable_addr)
{
sys_ppu_thread.Warning("sys_ppu_thread_get_join_state(isjoinable_addr=0x%x)", isjoinable_addr);
Memory.Write32(isjoinable_addr, GetCurrentPPUThread().IsJoinable());
vm::write32(isjoinable_addr, GetCurrentPPUThread().IsJoinable());
}
s32 sys_ppu_thread_set_priority(u64 thread_id, s32 prio)
@ -108,7 +108,7 @@ s32 sys_ppu_thread_get_priority(u64 thread_id, u32 prio_addr)
CPUThread* thr = Emu.GetCPU().GetThread(thread_id);
if(!thr) return CELL_ESRCH;
Memory.Write32(prio_addr, (s32)thr->GetPrio());
vm::write32(prio_addr, (s32)thr->GetPrio());
return CELL_OK;
}
@ -119,8 +119,8 @@ s32 sys_ppu_thread_get_stack_information(u32 info_addr)
declCPU();
Memory.Write32(info_addr, (u32)CPU.GetStackAddr());
Memory.Write32(info_addr + 4, CPU.GetStackSize());
vm::write32(info_addr, (u32)CPU.GetStackAddr());
vm::write32(info_addr + 4, CPU.GetStackSize());
return CELL_OK;
}
@ -204,7 +204,7 @@ void sys_ppu_thread_once(vm::ptr<std::atomic<be_t<u32>>> once_ctrl, u32 entry)
be_t<u32> old = be_t<u32>::MakeFromBE(se32(SYS_PPU_THREAD_ONCE_INIT));
if (once_ctrl->compare_exchange_weak(old, be_t<u32>::MakeFromBE(se32(SYS_PPU_THREAD_DONE_INIT))))
{
GetCurrentPPUThread().FastCall2(Memory.Read32(entry), Memory.Read32(entry + 4));
GetCurrentPPUThread().FastCall2(vm::read32(entry), vm::read32(entry + 4));
}
}

2
rpcs3/Emu/SysCalls/lv2/sys_process.cpp
View file

@ -279,7 +279,7 @@ s32 sys_process_wait_for_child2(u64 unk1, u64 unk2, u64 unk3, u64 unk4, u64 unk5
s32 sys_process_get_status(u64 unk)
{
sys_process.Todo("sys_process_get_status(unk=0x%llx)", unk);
//Memory.Write32(CPU.GPR[4], GetPPUThreadStatus(CPU));
//vm::write32(CPU.GPR[4], GetPPUThreadStatus(CPU));
return CELL_OK;
}

4
rpcs3/Emu/SysCalls/lv2/sys_time.cpp
View file

@ -77,8 +77,8 @@ s32 sys_time_get_current_time(u32 sec_addr, u32 nsec_addr)
u64 time = get_time();
Memory.Write64(sec_addr, time / timebase_frequency);
Memory.Write64(nsec_addr, (time % timebase_frequency) * 1000000000 / (s64)(timebase_frequency));
vm::write64(sec_addr, time / timebase_frequency);
vm::write64(nsec_addr, (time % timebase_frequency) * 1000000000 / (s64)(timebase_frequency));
return CELL_OK;
}

2
rpcs3/Emu/SysCalls/lv2/sys_vm.cpp
View file

@ -58,7 +58,7 @@ s32 sys_vm_memory_map(u32 vsize, u32 psize, u32 cid, u64 flag, u64 policy, u32 a
}
// Write a pointer for the allocated memory.
Memory.Write32(addr, current_ct->addr);
vm::write32(addr, current_ct->addr);
return CELL_OK;
}

4
rpcs3/Emu/System.cpp
View file

@ -345,7 +345,7 @@ void Emulator::Load()
//thread.AddArgv("-emu");
m_rsx_callback = (u32)Memory.MainMem.AllocAlign(4 * 4) + 4;
Memory.Write32(m_rsx_callback - 4, m_rsx_callback);
vm::write32(m_rsx_callback - 4, m_rsx_callback);
auto callback_data = vm::ptr<be_t<u32>>::make(m_rsx_callback);
callback_data[0] = ADDI(11, 0, 0x3ff);
@ -366,7 +366,7 @@ void Emulator::Load()
ppu_thr_stop_data[0] = SC(4);
ppu_thr_stop_data[1] = BCLR(0x10 | 0x04, 0, 0, 0);
Memory.Write64(Memory.PRXMem.AllocAlign(0x10000), 0xDEADBEEFABADCAFE);
vm::write64(Memory.PRXMem.AllocAlign(0x10000), 0xDEADBEEFABADCAFE);
}
break;

4
rpcs3/Gui/DisAsmFrame.cpp
View file

@ -170,7 +170,7 @@ public:
wxString::Format("%d thread: %d of %d", (int)id + 1, vsize, max_value));
disasm->dump_pc = sh_addr + off;
decoder->Decode(Memory.Read32(disasm->dump_pc));
decoder->Decode(vm::read32(disasm->dump_pc));
arr[id][sh].Add(fmt::FromUTF8(disasm->last_opcode));
@ -395,7 +395,7 @@ void DisAsmFrame::Dump(wxCommandEvent& WXUNUSED(event))
for(u64 addr=sh_addr; addr<sh_addr+sh_size; addr++, vsize++)
{
disasm->dump_pc = addr;
decoder->Decode(Memory.Read32(disasm->dump_pc));
decoder->Decode(vm::read32(disasm->dump_pc));
fd.Write("\t");
fd.Write(fmt::FromUTF8(disasm->last_opcode));
}

4
rpcs3/Gui/InstructionEditor.h
View file

@ -73,7 +73,7 @@ InstructionEditorDialog::InstructionEditorDialog(wxPanel *parent, u64 _pc, CPUTh
s_panel_margin_x->AddSpacer(12);
this->Connect(wxEVT_COMMAND_TEXT_UPDATED, wxCommandEventHandler(InstructionEditorDialog::updatePreview));
t2_instr->SetValue(wxString::Format("%08x", Memory.Read32(CPU->GetOffset() + pc)));
t2_instr->SetValue(wxString::Format("%08x", vm::read32(CPU->GetOffset() + pc)));
this->SetSizerAndFit(s_panel_margin_x);
@ -83,7 +83,7 @@ InstructionEditorDialog::InstructionEditorDialog(wxPanel *parent, u64 _pc, CPUTh
if (!t2_instr->GetValue().ToULong(&opcode, 16))
wxMessageBox("This instruction could not be parsed.\nNo changes were made.","Error");
else
Memory.Write32(CPU->GetOffset() + pc, (u32)opcode);
vm::write32(CPU->GetOffset() + pc, (u32)opcode);
}
}

2
rpcs3/Gui/MemoryViewer.cpp
View file

@ -202,7 +202,7 @@ void MemoryViewerPanel::ShowMemory()
if (Memory.IsGoodAddr(addr))
{
const u8 rmem = Memory.Read8(addr);
const u8 rmem = vm::read8(addr);
t_mem_hex_str += wxString::Format("%02x ", rmem);
const bool isPrintable = rmem >= 32 && rmem <= 126;
t_mem_ascii_str += isPrintable ? std::string(1, rmem) : ".";

4
rpcs3/Gui/RSXDebugger.cpp
View file

@ -268,7 +268,7 @@ void RSXDebugger::OnScrollMemory(wxMouseEvent& event)
u32 offset;
if(Memory.IsGoodAddr(m_addr))
{
u32 cmd = Memory.Read32(m_addr);
u32 cmd = vm::read32(m_addr);
u32 count = (cmd & (CELL_GCM_METHOD_FLAG_JUMP | CELL_GCM_METHOD_FLAG_CALL))
|| cmd == CELL_GCM_METHOD_FLAG_RETURN ? 0 : (cmd >> 18) & 0x7ff;
@ -382,7 +382,7 @@ void RSXDebugger::GetMemory()
if (ioAddr && Memory.IsGoodAddr(addr))
{
u32 cmd = Memory.Read32(addr);
u32 cmd = vm::read32(addr);
u32 count = (cmd >> 18) & 0x7ff;
m_list_commands->SetItem(i, 1, wxString::Format("%08x", cmd));
m_list_commands->SetItem(i, 3, wxString::Format("%d", count));

8
rpcs3/Loader/ELF64.cpp
View file

@ -437,7 +437,7 @@ bool ELF64Loader::LoadPhdrData(u64 offset)
LOG_NOTICE(LOADER, "*** unk1: 0x%x", stub.s_unk1.ToLE());
LOG_NOTICE(LOADER, "*** imports: %d", stub.s_imports.ToLE());
LOG_NOTICE(LOADER, "*** module name: %s [0x%x]", module_name.c_str(), stub.s_modulename.ToLE());
LOG_NOTICE(LOADER, "*** nid: 0x%016llx [0x%x]", Memory.Read64(stub.s_nid), stub.s_nid.ToLE());
LOG_NOTICE(LOADER, "*** nid: 0x%016llx [0x%x]", vm::read64(stub.s_nid), stub.s_nid.ToLE());
LOG_NOTICE(LOADER, "*** text: 0x%x", stub.s_text.ToLE());
#endif
static const u32 section = 4 * 3;
@ -446,8 +446,8 @@ bool ELF64Loader::LoadPhdrData(u64 offset)
for(u32 i=0; i<stub.s_imports; ++i)
{
const u32 nid = Memory.Read32(stub.s_nid + i*4);
const u32 text = Memory.Read32(stub.s_text + i*4);
const u32 nid = vm::read32(stub.s_nid + i*4);
const u32 text = vm::read32(stub.s_text + i*4);
if (module && !module->Load(nid))
{
@ -462,7 +462,7 @@ bool ELF64Loader::LoadPhdrData(u64 offset)
LOG_NOTICE(LOADER, "*** nid: 0x%x (0x%x)", nid, stub.s_nid + i*4);
LOG_NOTICE(LOADER, "*** text: 0x%x (0x%x)", text, stub.s_text + i*4);
#endif
Memory.Write32(stub.s_text + i*4, (u32)tbl + i*8);
vm::write32(stub.s_text + i*4, (u32)tbl + i*8);
auto out_tbl = vm::ptr<be_t<u32>>::make((u32)tbl + i * 8);
out_tbl[0] = (u32)dst + i*section;

1
rpcs3/rpcs3.vcxproj
View file

@ -209,6 +209,7 @@
<ClInclude Include="Gui\GameViewer.h" />
<ClInclude Include="Gui\GLGSFrame.h" />
<ClInclude Include="Gui\GSFrame.h" />
<ClInclude Include="Gui\InstructionEditor.h" />
<ClInclude Include="Gui\InterpreterDisAsm.h" />
<ClInclude Include="Gui\KernelExplorer.h" />
<ClInclude Include="Gui\MainFrame.h" />

3
rpcs3/rpcs3.vcxproj.filters
View file

@ -182,5 +182,8 @@
<ClInclude Include="Gui\MsgDialog.h">
<Filter>Gui</Filter>
</ClInclude>
<ClInclude Include="Gui\InstructionEditor.h">
<Filter>Gui</Filter>
</ClInclude>
</ItemGroup>
</Project>

196
rpcs3/stdafx.h
View file

@ -42,207 +42,11 @@ typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
static const u32 U32_MAX = 0xffffffffu;
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef int64_t s64;
static const s32 S32_MIN = (s32)0x80000000u;
static const s32 S32_MAX = 0x7fffffff;
union u128
{
struct
{
u64 hi;
u64 lo;
};
u64 _u64[2];
u32 _u32[4];
u16 _u16[8];
u8 _u8[16];
operator u64() const { return _u64[0]; }
operator u32() const { return _u32[0]; }
operator u16() const { return _u16[0]; }
operator u8() const { return _u8[0]; }
operator bool() const { return _u64[0] != 0 || _u64[1] != 0; }
static u128 From128(u64 hi, u64 lo)
{
u128 ret = { hi, lo };
return ret;
}
static u128 From64(u64 src)
{
u128 ret = { 0, src };
return ret;
}
static u128 From32(u32 src)
{
u128 ret;
ret._u32[0] = src;
ret._u32[1] = 0;
ret._u32[2] = 0;
ret._u32[3] = 0;
return ret;
}
static u128 FromBit(u32 bit)
{
u128 ret;
if (bit < 64)
{
ret.hi = 0;
ret.lo = (u64)1 << bit;
}
else if (bit < 128)
{
ret.hi = (u64)1 << (bit - 64);
ret.lo = 0;
}
else
{
ret.hi = 0;
ret.lo = 0;
}
return ret;
}
bool operator == (const u128& right) const
{
return (lo == right.lo) && (hi == right.hi);
}
bool operator != (const u128& right) const
{
return (lo != right.lo) || (hi != right.hi);
}
u128 operator | (const u128& right) const
{
return From128(hi | right.hi, lo | right.lo);
}
u128 operator & (const u128& right) const
{
return From128(hi & right.hi, lo & right.lo);
}
u128 operator ^ (const u128& right) const
{
return From128(hi ^ right.hi, lo ^ right.lo);
}
u128 operator ~ () const
{
return From128(~hi, ~lo);
}
static __forceinline u128 byteswap(const u128 val)
{
u128 ret;
ret.lo = _byteswap_uint64(val.hi);
ret.hi = _byteswap_uint64(val.lo);
return ret;
}
};
union s128
{
struct
{
s64 hi;
s64 lo;
};
u64 _i64[2];
u32 _i32[4];
u16 _i16[8];
u8 _i8[16];
operator s64() const { return _i64[0]; }
operator s32() const { return _i32[0]; }
operator s16() const { return _i16[0]; }
operator s8() const { return _i8[0]; }
operator bool() const { return _i64[0] != 0 || _i64[1] != 0; }
static s128 From64(s64 src)
{
s128 ret = { src, 0 };
return ret;
}
static s128 From32(s32 src)
{
s128 ret;
ret._i32[0] = src;
ret._i32[1] = 0;
ret.hi = 0;
return ret;
}
bool operator == (const s128& right) const
{
return (lo == right.lo) && (hi == right.hi);
}
bool operator != (const s128& right) const
{
return (lo != right.lo) || (hi != right.hi);
}
};
//TODO: SSE style
/*
struct u128
{
__m128 m_val;
u128 GetValue128()
{
u128 ret;
_mm_store_ps( (float*)&ret, m_val );
return ret;
}
u64 GetValue64()
{
u64 ret;
_mm_store_ps( (float*)&ret, m_val );
return ret;
}
u32 GetValue32()
{
u32 ret;
_mm_store_ps( (float*)&ret, m_val );
return ret;
}
u16 GetValue16()
{
u16 ret;
_mm_store_ps( (float*)&ret, m_val );
return ret;
}
u8 GetValue8()
{
u8 ret;
_mm_store_ps( (float*)&ret, m_val );
return ret;
}
};
*/
#define AlignAddr(addr, align) (((addr) + ((align) - 1)) & ~((align) - 1))
#include "Utilities/StrFmt.h"