diff --git a/rpcs3/Emu/RSX/VK/VKGSRender.cpp b/rpcs3/Emu/RSX/VK/VKGSRender.cpp
index da14209c74..246d504333 100644
--- a/rpcs3/Emu/RSX/VK/VKGSRender.cpp
+++ b/rpcs3/Emu/RSX/VK/VKGSRender.cpp
@@ -1608,6 +1608,15 @@ bool VKGSRender::load_program()
 			rsx::method_registers.msaa_enabled(),
 			rsx::method_registers.msaa_alpha_to_coverage_enabled(),
 			alpha_to_one_enable);
+
+		if (const auto chip_family = vk::get_chip_family();
+			chip_family == vk::chip_class::AMD_navi1x ||
+			chip_family == vk::chip_class::AMD_navi2x)
+		{
+			// NAVI family has a GPU bug with MSAA where shading rate is not correctly initialized if left disabled
+			// Manually initialize it and set it to spec default (full shading)
+			properties.state.set_multisample_shading_rate(1.f);
+		}
 	}
 
 	properties.renderpass_key = m_current_renderpass_key;
diff --git a/rpcs3/Emu/RSX/VK/VKHelpers.cpp b/rpcs3/Emu/RSX/VK/VKHelpers.cpp
index 2743d9ab3a..e0b53641f7 100644
--- a/rpcs3/Emu/RSX/VK/VKHelpers.cpp
+++ b/rpcs3/Emu/RSX/VK/VKHelpers.cpp
@@ -31,8 +31,9 @@ namespace vk
 		table.add(0x66A0, 0x66AF, chip_class::AMD_vega); // Vega20
 		table.add(0x15DD, chip_class::AMD_vega); // Raven Ridge
 		table.add(0x15D8, chip_class::AMD_vega); // Raven Ridge
-		table.add(0x7310, 0x731F, chip_class::AMD_navi); // Navi10
-		table.add(0x7340, 0x734F, chip_class::AMD_navi); // Navi14
+		table.add(0x7310, 0x731F, chip_class::AMD_navi1x); // Navi10
+		table.add(0x7340, 0x734F, chip_class::AMD_navi1x); // Navi14
+		table.add(0x73A0, 0x73BF, chip_class::AMD_navi2x); // Sienna cichlid
 
 		return table;
 	}();
diff --git a/rpcs3/Emu/RSX/VK/VKHelpers.h b/rpcs3/Emu/RSX/VK/VKHelpers.h
index 12bd492d4d..7830133153 100644
--- a/rpcs3/Emu/RSX/VK/VKHelpers.h
+++ b/rpcs3/Emu/RSX/VK/VKHelpers.h
@@ -85,7 +85,8 @@ namespace vk
 		AMD_gcn_generic,
 		AMD_polaris,
 		AMD_vega,
-		AMD_navi,
+		AMD_navi1x,
+		AMD_navi2x,
 		NV_generic,
 		NV_kepler,
 		NV_maxwell,