diff --git a/rpcs3/Emu/RSX/RSXThread.cpp b/rpcs3/Emu/RSX/RSXThread.cpp
index 10843ac584..c2d22bb7a1 100644
--- a/rpcs3/Emu/RSX/RSXThread.cpp
+++ b/rpcs3/Emu/RSX/RSXThread.cpp
@@ -1053,62 +1053,23 @@ namespace rsx
 			fmt::throw_exception("Unknown framebuffer context 0x%x" HERE, (u32)context);
 		}
 
-		auto check_swizzled_render = [&]()
-		{
-			// Packed rasterization with optimal memory layout
-			// Pitch has to be packed for all active render targets, i.e 64
-			// Formats also seemingly need matching depth and color pitch if both are active
-
-			if (color_buffer_unused)
-			{
-				// Check only depth
-				return (layout.zeta_pitch == 64);
-			}
-			else if (depth_buffer_unused)
-			{
-				// Check only color
-				for (const auto& index : rsx::utility::get_rtt_indexes(layout.target))
-				{
-					if (layout.color_pitch[index] != 64)
-					{
-						return false;
-					}
-				}
-
-				return true;
-			}
-
-			if (depth_texel_size != color_texel_size)
-			{
-				// Both depth and color exist, but pixel size differs
-				return false;
-			}
-			else
-			{
-				// Qualifies, but only if all the pitch values are disabled (64)
-				// Both depth and color are assumed to exist in this case, unless proven otherwise
-				if (layout.zeta_pitch != 64)
-				{
-					return false;
-				}
-
-				for (const auto& index : rsx::utility::get_rtt_indexes(layout.target))
-				{
-					if (layout.color_pitch[index] != 64)
-					{
-						return false;
-					}
-				}
-
-				return true;
-			}
-		};
-
 		// Swizzled render does tight packing of bytes
-		const bool packed_render = check_swizzled_render();
+		bool packed_render = false;
 		u32 minimum_color_pitch = 64u;
 		u32 minimum_zeta_pitch = 64u;
 
+		switch (const auto mode = rsx::method_registers.surface_type())
+		{
+		default:
+			LOG_ERROR(RSX, "Unknown raster mode 0x%x", (u32)mode);
+			[[fallthrough]];
+		case rsx::surface_raster_type::linear:
+			break;
+		case rsx::surface_raster_type::swizzle:
+			packed_render = true;
+			break;
+		};
+
 		if (!packed_render)
 		{
 			// Well, this is a write operation either way (clearing or drawing)
diff --git a/rpcs3/Emu/RSX/gcm_enums.h b/rpcs3/Emu/RSX/gcm_enums.h
index 479fa60697..a101863763 100644
--- a/rpcs3/Emu/RSX/gcm_enums.h
+++ b/rpcs3/Emu/RSX/gcm_enums.h
@@ -61,6 +61,12 @@ namespace rsx
 
 	surface_depth_format to_surface_depth_format(u8 in);
 
+	enum class surface_raster_type : u8
+	{
+		linear = 1,
+		swizzle = 2,
+	};
+
 	enum class surface_antialiasing : u8
 	{
 		center_1_sample,
diff --git a/rpcs3/Emu/RSX/rsx_decode.h b/rpcs3/Emu/RSX/rsx_decode.h
index 954dd31cf5..11782aacd3 100644
--- a/rpcs3/Emu/RSX/rsx_decode.h
+++ b/rpcs3/Emu/RSX/rsx_decode.h
@@ -3530,6 +3530,7 @@ struct registers_decoder<NV4097_SET_SURFACE_FORMAT>
 			u32 raw_value;
 			bitfield_decoder_t<0, 5> color_fmt;
 			bitfield_decoder_t<5, 3> depth_fmt;
+			bitfield_decoder_t<8, 4> type;
 			bitfield_decoder_t<12, 4> antialias;
 			bitfield_decoder_t<16, 8> log2width;
 			bitfield_decoder_t<24, 8> log2height;
@@ -3547,6 +3548,11 @@ struct registers_decoder<NV4097_SET_SURFACE_FORMAT>
 			return to_surface_depth_format(m_data.depth_fmt);
 		}
 
+		surface_raster_type type() const
+		{
+			return static_cast<surface_raster_type>(u8(m_data.type));
+		}
+
 		surface_antialiasing antialias() const
 		{
 			return to_surface_antialiasing(m_data.antialias);
diff --git a/rpcs3/Emu/RSX/rsx_methods.h b/rpcs3/Emu/RSX/rsx_methods.h
index 531a893f59..96d62686c4 100644
--- a/rpcs3/Emu/RSX/rsx_methods.h
+++ b/rpcs3/Emu/RSX/rsx_methods.h
@@ -1243,6 +1243,11 @@ namespace rsx
 			return decode<NV4097_SET_SURFACE_FORMAT>().depth_fmt();
 		}
 
+		surface_raster_type surface_type() const
+		{
+			return decode<NV4097_SET_SURFACE_FORMAT>().type();
+		}
+
 		surface_antialiasing surface_antialias() const
 		{
 			return decode<NV4097_SET_SURFACE_FORMAT>().antialias();