mirror of
https://github.com/RPCS3/rpcs3.git
synced 2025-04-20 19:45:20 +00:00
Removed unnecessary code
This commit is contained in:
Nekotekina
parent
22af341ad3
commit
fc2a45d6d6
5 changed files with 5 additions and 513 deletions
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@ -23,9 +23,6 @@ void fmt_class_string<ppu_attr>::format(std::string& out, u64 arg)
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case ppu_attr::known_size: return "known_size";
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case ppu_attr::no_return: return "no_return";
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case ppu_attr::no_size: return "no_size";
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case ppu_attr::uses_r0: return "uses_r0";
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case ppu_attr::entry_point: return "entry_point";
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case ppu_attr::complex_stack: return "complex_stack";
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case ppu_attr::__bitset_enum_max: break;
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}
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@ -1037,15 +1034,6 @@ std::vector<ppu_function> ppu_analyse(const std::vector<std::pair<u32, u32>>& se
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func.size = len;
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}
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if (ptr + 3 <= fend &&
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(ptr[0] & 0xffff0000) == LI(r0, 0) &&
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(ptr[1] & 0xffff0000) == ORIS(r0, r0, 0) &&
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(ptr[2] & 0xfc000003) == B({}, {}, {}))
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{
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// Import stub with r0 usage
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func.attr += ppu_attr::uses_r0;
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}
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// TODO: detect no_return, scribe more TODOs
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// Acknowledge completion
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@ -14,12 +14,6 @@ enum class ppu_attr : u32
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known_size,
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no_return,
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no_size,
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uses_r0,
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entry_point,
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complex_stack,
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special,
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//call_use_context,
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//call_trace,
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__bitset_enum_max
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};
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@ -536,422 +530,6 @@ struct ppu_itype
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}
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};
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// PPU Instruction Flags
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struct ppu_iflag
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{
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// Various flags (TODO)
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enum : u32
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{
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write_rd = 1 << 0,
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write_ra = 1 << 1,
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read_ra = 1 << 2,
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read_rb = 1 << 3,
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read_rs = 1 << 4,
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write_vd = 1 << 5,
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read_va = 1 << 6,
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read_vb = 1 << 7,
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read_vc = 1 << 8,
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read_vs = 1 << 9,
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write_frd = 1 << 10,
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read_fra = 1 << 11,
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read_frb = 1 << 12,
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read_frc = 1 << 13,
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read_frs = 1 << 14,
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rw_all = 1 << 15,
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};
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enum flags : u32
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{
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UNK = 0,
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MFVSCR = 0,
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MTVSCR = 0,
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VADDCUW = 0,
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VADDFP = 0,
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VADDSBS = 0,
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VADDSHS = 0,
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VADDSWS = 0,
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VADDUBM = 0,
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VADDUBS = 0,
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VADDUHM = 0,
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VADDUHS = 0,
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VADDUWM = 0,
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VADDUWS = 0,
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VAND = 0,
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VANDC = 0,
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VAVGSB = 0,
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VAVGSH = 0,
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VAVGSW = 0,
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VAVGUB = 0,
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VAVGUH = 0,
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VAVGUW = 0,
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VCFSX = 0,
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VCFUX = 0,
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VCMPBFP = 0,
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VCMPEQFP = 0,
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VCMPEQUB = 0,
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VCMPEQUH = 0,
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VCMPEQUW = 0,
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VCMPGEFP = 0,
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VCMPGTFP = 0,
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VCMPGTSB = 0,
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VCMPGTSH = 0,
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VCMPGTSW = 0,
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VCMPGTUB = 0,
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VCMPGTUH = 0,
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VCMPGTUW = 0,
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VCTSXS = 0,
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VCTUXS = 0,
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VEXPTEFP = 0,
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VLOGEFP = 0,
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VMADDFP = 0,
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VMAXFP = 0,
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VMAXSB = 0,
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VMAXSH = 0,
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VMAXSW = 0,
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VMAXUB = 0,
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VMAXUH = 0,
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VMAXUW = 0,
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VMHADDSHS = 0,
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VMHRADDSHS = 0,
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VMINFP = 0,
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VMINSB = 0,
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VMINSH = 0,
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VMINSW = 0,
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VMINUB = 0,
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VMINUH = 0,
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VMINUW = 0,
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VMLADDUHM = 0,
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VMRGHB = 0,
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VMRGHH = 0,
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VMRGHW = 0,
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VMRGLB = 0,
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VMRGLH = 0,
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VMRGLW = 0,
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VMSUMMBM = 0,
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VMSUMSHM = 0,
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VMSUMSHS = 0,
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VMSUMUBM = 0,
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VMSUMUHM = 0,
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VMSUMUHS = 0,
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VMULESB = 0,
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VMULESH = 0,
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VMULEUB = 0,
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VMULEUH = 0,
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VMULOSB = 0,
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VMULOSH = 0,
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VMULOUB = 0,
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VMULOUH = 0,
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VNMSUBFP = 0,
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VNOR = 0,
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VOR = 0,
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VPERM = 0,
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VPKPX = 0,
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VPKSHSS = 0,
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VPKSHUS = 0,
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VPKSWSS = 0,
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VPKSWUS = 0,
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VPKUHUM = 0,
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VPKUHUS = 0,
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VPKUWUM = 0,
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VPKUWUS = 0,
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VREFP = 0,
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VRFIM = 0,
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VRFIN = 0,
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VRFIP = 0,
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VRFIZ = 0,
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VRLB = 0,
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VRLH = 0,
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VRLW = 0,
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VRSQRTEFP = 0,
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VSEL = 0,
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VSL = 0,
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VSLB = 0,
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VSLDOI = 0,
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VSLH = 0,
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VSLO = 0,
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VSLW = 0,
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VSPLTB = 0,
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VSPLTH = 0,
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VSPLTISB = 0,
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VSPLTISH = 0,
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VSPLTISW = 0,
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VSPLTW = 0,
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VSR = 0,
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VSRAB = 0,
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VSRAH = 0,
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VSRAW = 0,
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VSRB = 0,
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VSRH = 0,
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VSRO = 0,
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VSRW = 0,
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VSUBCUW = 0,
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VSUBFP = 0,
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VSUBSBS = 0,
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VSUBSHS = 0,
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VSUBSWS = 0,
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VSUBUBM = 0,
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VSUBUBS = 0,
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VSUBUHM = 0,
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VSUBUHS = 0,
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VSUBUWM = 0,
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VSUBUWS = 0,
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VSUMSWS = 0,
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VSUM2SWS = 0,
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VSUM4SBS = 0,
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VSUM4SHS = 0,
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VSUM4UBS = 0,
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VUPKHPX = 0,
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VUPKHSB = 0,
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VUPKHSH = 0,
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VUPKLPX = 0,
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VUPKLSB = 0,
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VUPKLSH = 0,
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VXOR = 0,
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TDI = read_ra,
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TWI = read_ra,
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MULLI = read_ra,
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SUBFIC = read_ra,
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CMPLI = read_ra,
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CMPI = read_ra,
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ADDIC = read_ra,
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ADDI = read_ra,
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ADDIS = read_ra,
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BC = 0,
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SC = 0,
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B = 0,
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MCRF = 0,
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BCLR = 0,
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CRNOR = 0,
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CRANDC = 0,
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ISYNC = 0,
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CRXOR = 0,
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CRNAND = 0,
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CRAND = 0,
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CREQV = 0,
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CRORC = 0,
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CROR = 0,
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BCCTR = 0,
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RLWIMI = read_ra | read_rs,
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RLWINM = read_rs,
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RLWNM = read_rs | read_rb,
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ORI = read_rs,
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ORIS = read_rs,
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XORI = read_rs,
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XORIS = read_rs,
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ANDI = read_rs,
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ANDIS = read_rs,
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RLDICL = read_rs,
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RLDICR = read_rs,
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RLDIC = read_rs,
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RLDIMI = read_ra | read_rs,
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RLDCL = read_rs | read_rb,
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RLDCR = read_rs | read_rb,
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CMP = read_ra | read_rb,
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TW = read_ra | read_rb,
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LVSL = read_ra | read_rb,
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LVEBX = read_ra | read_rb,
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SUBFC = read_ra | read_rb,
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ADDC = read_ra | read_rb,
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MULHDU = read_ra | read_rb,
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MULHWU = read_ra | read_rb,
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MFOCRF = 0,
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LWARX = read_ra | read_rb,
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LDX = read_ra | read_rb,
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LWZX = read_ra | read_rb,
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SLW = read_rs | read_rb,
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CNTLZW = read_rs,
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SLD = read_rs | read_rb,
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AND = read_rs | read_rb,
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CMPL = read_ra | read_rb,
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LVSR = read_ra | read_rb,
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LVEHX = read_ra | read_rb,
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SUBF = read_ra | read_rb,
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LDUX = read_ra | read_rb,
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DCBST = 0,
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LWZUX = read_ra | read_rb,
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CNTLZD = read_rs,
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ANDC = read_rs | read_rb,
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TD = read_ra | read_rb,
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LVEWX = read_ra | read_rb,
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MULHD = read_ra | read_rb,
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MULHW = read_ra | read_rb,
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LDARX = read_ra | read_rb,
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DCBF = 0,
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LBZX = read_ra | read_rb,
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LVX = read_ra | read_rb,
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NEG = read_ra,
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LBZUX = read_ra | read_rb,
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NOR = read_rs | read_rb,
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STVEBX = read_ra | read_rb,
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SUBFE = read_ra | read_rb,
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ADDE = read_ra | read_rb,
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MTOCRF = read_rs,
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STDX = read_rs | read_ra | read_rb,
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STWCX = read_rs | read_ra | read_rb,
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STWX = read_rs | read_ra | read_rb,
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STVEHX = read_ra | read_rb,
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STDUX = read_rs | read_ra | read_rb,
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STWUX = read_rs | read_ra | read_rb,
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STVEWX = read_ra | read_rb,
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SUBFZE = read_ra,
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ADDZE = read_ra,
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STDCX = read_rs | read_ra | read_rb,
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STBX = read_rs | read_ra | read_rb,
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STVX = read_ra | read_rb,
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SUBFME = read_ra,
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MULLD = read_ra | read_rb,
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ADDME = read_ra | read_rb,
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MULLW = read_ra | read_rb,
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DCBTST = 0,
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STBUX = read_rs | read_ra | read_rb,
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ADD = read_ra | read_rb,
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DCBT = 0,
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LHZX = read_ra | read_rb,
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EQV = read_rs | read_rb,
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ECIWX = read_ra | read_rb,
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LHZUX = read_ra | read_rb,
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XOR = read_rs | read_rb,
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MFSPR = 0,
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LWAX = read_ra | read_rb,
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DST = 0,
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LHAX = read_ra | read_rb,
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LVXL = LVX,
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MFTB = MFSPR,
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LWAUX = read_ra | read_rb,
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DSTST = 0,
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LHAUX = read_ra | read_rb,
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STHX = read_rs | read_ra | read_rb,
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ORC = read_rs | read_rb,
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ECOWX = read_rs | read_ra | read_rb,
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STHUX = read_rs | read_ra | read_rb,
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OR = read_rs | read_rb,
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DIVDU = read_ra | read_rb,
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DIVWU = read_ra | read_rb,
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MTSPR = read_rs,
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DCBI = 0,
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NAND = read_rs | read_rb,
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STVXL = STVX,
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DIVD = read_ra | read_rb,
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DIVW = read_ra | read_rb,
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LVLX = read_ra | read_rb,
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LDBRX = read_ra | read_rb,
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LSWX = read_ra | read_rb | rw_all,
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LWBRX = read_ra | read_rb,
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LFSX = read_ra | read_rb,
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SRW = read_rs | read_rb,
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SRD = read_rs | read_rb,
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LVRX = read_ra | read_rb,
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LSWI = rw_all,
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LFSUX = read_ra | read_rb,
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SYNC = 0,
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LFDX = read_ra | read_rb,
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LFDUX = read_ra | read_rb,
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STVLX = read_ra | read_rb,
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STDBRX = read_rs | read_ra | read_rb,
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STSWX = rw_all,
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STWBRX = read_rs | read_ra | read_rb,
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STFSX = read_ra | read_rb,
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STVRX = read_ra | read_rb,
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STFSUX = read_ra | read_rb,
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STSWI = rw_all,
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STFDX = read_ra | read_rb,
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STFDUX = read_ra | read_rb,
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LVLXL = LVLX,
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LHBRX = read_ra | read_rb,
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SRAW = read_rs | read_rb,
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SRAD = read_rs | read_rb,
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LVRXL = LVRX,
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DSS = 0,
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SRAWI = read_rs,
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SRADI = read_rs,
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EIEIO = 0,
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STVLXL = STVLX,
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STHBRX = read_rs | read_ra | read_rb,
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EXTSH = read_rs,
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STVRXL = STVRX,
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EXTSB = read_rs,
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STFIWX = read_ra | read_rb,
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EXTSW = read_rs,
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ICBI = 0,
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DCBZ = read_ra | read_rb,
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LWZ = read_ra,
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LWZU = read_ra,
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LBZ = read_ra,
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LBZU = read_ra,
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STW = read_rs | read_ra,
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STWU = read_rs | read_ra,
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STB = read_rs | read_ra,
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STBU = read_rs | read_ra,
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LHZ = read_ra,
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LHZU = read_ra,
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LHA = read_ra,
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LHAU = read_ra,
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STH = read_rs | read_ra,
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STHU = read_rs | read_ra,
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LMW = rw_all,
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STMW = rw_all,
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LFS = read_ra,
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LFSU = read_ra,
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LFD = read_ra,
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LFDU = read_ra,
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STFS = read_ra,
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STFSU = read_ra,
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STFD = read_ra,
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STFDU = read_ra,
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LD = read_ra,
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LDU = read_ra,
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LWA = read_ra,
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STD = read_rs | read_ra,
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STDU = read_rs | read_ra,
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FDIVS = 0,
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FSUBS = 0,
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FADDS = 0,
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FSQRTS = 0,
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FRES = 0,
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FMULS = 0,
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FMADDS = 0,
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FMSUBS = 0,
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FNMSUBS = 0,
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FNMADDS = 0,
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MTFSB1 = 0,
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MCRFS = 0,
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MTFSB0 = 0,
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MTFSFI = 0,
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MFFS = 0,
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MTFSF = 0,
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FCMPU = 0,
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FRSP = 0,
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FCTIW = 0,
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FCTIWZ = 0,
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FDIV = 0,
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FSUB = 0,
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FADD = 0,
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FSQRT = 0,
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FSEL = 0,
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FMUL = 0,
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FRSQRTE = 0,
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FMSUB = 0,
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FMADD = 0,
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FNMSUB = 0,
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FNMADD = 0,
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FCMPO = 0,
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FNEG = 0,
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FMR = 0,
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FNABS = 0,
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FABS = 0,
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FCTID = 0,
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FCTIDZ = 0,
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FCFID = 0,
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};
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// Enable address-of operator for ppu_decoder<>
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friend constexpr flags operator &(flags value)
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{
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return value;
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}
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};
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// Encode instruction name: 6 bits per character (0x20..0x5f), max 10
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static constexpr u64 ppu_iname_encode(const char* ptr, u64 value = 0)
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{
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|
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|
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@ -5,28 +5,7 @@
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#include <cmath>
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inline u64 dup32(const u32 x) { return x | static_cast<u64>(x) << 32; }
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#if defined(__GNUG__)
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inline u64 UMULH64(u64 a, u64 b)
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||||
{
|
||||
u64 result;
|
||||
__asm__("mulq %[b]" : "=d" (result) : [a] "a" (a), [b] "rm" (b));
|
||||
return result;
|
||||
}
|
||||
|
||||
inline s64 MULH64(s64 a, s64 b)
|
||||
{
|
||||
s64 result;
|
||||
__asm__("imulq %[b]" : "=d" (result) : [a] "a" (a), [b] "rm" (b));
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||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
#define UMULH64 __umulh
|
||||
#define MULH64 __mulh
|
||||
#endif
|
||||
inline u64 dup32(u32 x) { return x | static_cast<u64>(x) << 32; }
|
||||
|
||||
// Write values to CR field
|
||||
inline void ppu_cr_set(ppu_thread& ppu, u32 field, bool le, bool gt, bool eq, bool so)
|
||||
|
|
@ -3145,7 +3124,7 @@ bool ppu_interpreter::SUBFC(ppu_thread& ppu, ppu_opcode_t op)
|
|||
|
||||
bool ppu_interpreter::MULHDU(ppu_thread& ppu, ppu_opcode_t op)
|
||||
{
|
||||
ppu.gpr[op.rd] = UMULH64(ppu.gpr[op.ra], ppu.gpr[op.rb]);
|
||||
ppu.gpr[op.rd] = umulh64(ppu.gpr[op.ra], ppu.gpr[op.rb]);
|
||||
if (UNLIKELY(op.rc)) ppu_cr_set<s64>(ppu, 0, ppu.gpr[op.rd], 0);
|
||||
return true;
|
||||
}
|
||||
|
|
@ -3343,7 +3322,7 @@ bool ppu_interpreter::LVEWX(ppu_thread& ppu, ppu_opcode_t op)
|
|||
|
||||
bool ppu_interpreter::MULHD(ppu_thread& ppu, ppu_opcode_t op)
|
||||
{
|
||||
ppu.gpr[op.rd] = MULH64(ppu.gpr[op.ra], ppu.gpr[op.rb]);
|
||||
ppu.gpr[op.rd] = mulh64(ppu.gpr[op.ra], ppu.gpr[op.rb]);
|
||||
if (UNLIKELY(op.rc)) ppu_cr_set<s64>(ppu, 0, ppu.gpr[op.rd], 0);
|
||||
return true;
|
||||
}
|
||||
|
|
@ -3579,7 +3558,7 @@ bool ppu_interpreter::MULLD(ppu_thread& ppu, ppu_opcode_t op)
|
|||
ppu.gpr[op.rd] = (s64)(RA * RB);
|
||||
if (UNLIKELY(op.oe))
|
||||
{
|
||||
const s64 high = MULH64(RA, RB);
|
||||
const s64 high = mulh64(RA, RB);
|
||||
ppu_ov_set(ppu, high != s64(ppu.gpr[op.rd]) >> 63);
|
||||
}
|
||||
if (UNLIKELY(op.rc)) ppu_cr_set<s64>(ppu, 0, ppu.gpr[op.rd], 0);
|
||||
|
|
|
|||
|
|
@ -1229,7 +1229,7 @@ static void ppu_initialize2(jit_compiler& jit, const ppu_module& module_part, co
|
|||
return;
|
||||
}
|
||||
|
||||
if (module_part.funcs[fi].size && !test(module_part.funcs[fi].attr & ppu_attr::special))
|
||||
if (module_part.funcs[fi].size)
|
||||
{
|
||||
// Update dialog
|
||||
Emu.CallAfter([=, max = module_part.funcs.size()]()
|
||||
|
|
|
|||
|
|
@ -11,59 +11,6 @@ using namespace llvm;
|
|||
|
||||
const ppu_decoder<PPUTranslator> s_ppu_decoder;
|
||||
|
||||
/* Interpreter Call Macro (unused) */
|
||||
|
||||
#define VEC3OP(name) SetVr(op.vd, Call(GetType<u32[4]>(), "__vec3op",\
|
||||
m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
|
||||
GetVr(op.va, VrType::vi32),\
|
||||
GetVr(op.vb, VrType::vi32),\
|
||||
GetVr(op.vc, VrType::vi32)))
|
||||
|
||||
#define VEC2OP(name) SetVr(op.vd, Call(GetType<u32[4]>(), "__vec3op",\
|
||||
m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
|
||||
GetVr(op.va, VrType::vi32),\
|
||||
GetVr(op.vb, VrType::vi32),\
|
||||
GetUndef<u32[4]>()))
|
||||
|
||||
#define VECIOP(name) SetVr(op.vd, Call(GetType<u32[4]>(), "__veciop",\
|
||||
m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
|
||||
m_ir->getInt32(op.opcode),\
|
||||
GetVr(op.vb, VrType::vi32)))
|
||||
|
||||
#define FPOP(name) SetFpr(op.frd, Call(GetType<f64>(), "__fpop",\
|
||||
m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
|
||||
GetFpr(op.fra),\
|
||||
GetFpr(op.frb),\
|
||||
GetFpr(op.frc)))
|
||||
|
||||
#define AIMMOP(name) SetGpr(op.ra, Call(GetType<u64>(), "__aimmop",\
|
||||
m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
|
||||
m_ir->getInt32(op.opcode),\
|
||||
GetGpr(op.rs)))
|
||||
|
||||
#define AIMMBOP(name) SetGpr(op.ra, Call(GetType<u64>(), "__aimmbop",\
|
||||
m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
|
||||
m_ir->getInt32(op.opcode),\
|
||||
GetGpr(op.rs),\
|
||||
GetGpr(op.rb)))
|
||||
|
||||
#define AAIMMOP(name) SetGpr(op.ra, Call(GetType<u64>(), "__aaimmop",\
|
||||
m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
|
||||
m_ir->getInt32(op.opcode),\
|
||||
GetGpr(op.rs),\
|
||||
GetGpr(op.ra)))
|
||||
|
||||
#define IMMAOP(name) SetGpr(op.rd, Call(GetType<u64>(), "__immaop",\
|
||||
m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
|
||||
m_ir->getInt32(op.opcode),\
|
||||
GetGpr(op.ra)))
|
||||
|
||||
#define IMMABOP(name) SetGpr(op.rd, Call(GetType<u64>(), "__immabop",\
|
||||
m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
|
||||
m_ir->getInt32(op.opcode),\
|
||||
GetGpr(op.ra),\
|
||||
GetGpr(op.rb)))
|
||||
|
||||
PPUTranslator::PPUTranslator(LLVMContext& context, Module* module, const ppu_module& info)
|
||||
: m_context(context)
|
||||
, m_module(module)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue