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Add missing ICBI instruction.
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parent
9290453d2e
commit
ff89e06fd6
4 changed files with 10 additions and 4 deletions
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@ -1784,7 +1784,10 @@ private:
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{
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DisAsm_R2_RC("extsw", ra, rs, rc);
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}
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/*0x3d6*///ICBI
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void ICBI(u32 ra, u32 rb)
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{
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DisAsm_R2("icbi", ra, rb);
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}
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void DCBZ(u32 ra, u32 rs)
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{
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DisAsm_R2("dcbz", ra, rs);
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@ -571,7 +571,7 @@ namespace PPU_instr
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/*0x3ba*/bind_instr(g1f_list, EXTSB, RA, RS, RC);
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/*0x3d7*/bind_instr(g1f_list, STFIWX, FRS, RA, RB);
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/*0x3da*/bind_instr(g1f_list, EXTSW, RA, RS, RC);
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/*0x3d6*///ICBI
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/*0x3d6*/bind_instr(g1f_list, ICBI, RA, RB);
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/*0x3f6*/bind_instr(g1f_list, DCBZ, RA, RB);
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bind_instr(g3a_list, LD, RD, RA, DS);
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@ -3291,7 +3291,10 @@ private:
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//CPU.XER.CA = ((s64)CPU.GPR[ra] < 0); // ???
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if(rc) CPU.UpdateCR0<s32>(CPU.GPR[ra]);
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}
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/*0x3d6*///ICBI
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void ICBI(u32 ra, u32 rs)
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{
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// Clear jit for the specified block? Nothing to do in the interpreter.
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}
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void DCBZ(u32 ra, u32 rs)
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{
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//UNK("dcbz", false);
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@ -782,7 +782,7 @@ public:
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virtual void EXTSB(u32 ra, u32 rs, bool rc) = 0;
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virtual void STFIWX(u32 frs, u32 ra, u32 rb) = 0;
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virtual void EXTSW(u32 ra, u32 rs, bool rc) = 0;
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//ICBI
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virtual void ICBI(u32 ra, u32 rb) = 0;
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virtual void DCBZ(u32 ra, u32 rb) = 0;
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virtual void LWZ(u32 rd, u32 ra, s32 d) = 0;
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virtual void LWZU(u32 rd, u32 ra, s32 d) = 0;
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