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https://github.com/shadps4-emu/shadPS4.git
synced 2025-04-22 04:24:44 +00:00
fix for components mapping; missing prim type
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parent
3403e5a92a
commit
097a68a695
6 changed files with 17 additions and 10 deletions
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@ -25,6 +25,7 @@ static constexpr spv::ExecutionMode GetInputPrimitiveType(AmdGpu::PrimitiveType
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case AmdGpu::PrimitiveType::LineList:
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return spv::ExecutionMode::InputLines;
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case AmdGpu::PrimitiveType::TriangleList:
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case AmdGpu::PrimitiveType::TriangleStrip:
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return spv::ExecutionMode::Triangles;
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default:
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UNREACHABLE();
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@ -322,6 +323,7 @@ std::vector<u32> EmitSPIRV(const Profile& profile, const RuntimeInfo& runtime_in
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break;
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}
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PatchPhiNodes(program, ctx);
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binding.user_data += program.info.ud_mask.NumRegs();
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return ctx.Assemble();
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}
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@ -35,7 +35,7 @@ CopyShaderData ParseCopyShader(const std::span<const u32>& code) {
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for (int i = 0; i < inst.src_count; ++i) {
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const auto ofs = offsets[inst.src[i].code];
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if (ofs != -1) {
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data.attr_map[ofs] = semantic;
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data.attr_map[ofs] = {semantic, i};
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if (semantic > last_attr) {
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last_attr = semantic;
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}
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@ -12,7 +12,7 @@
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namespace Shader {
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struct CopyShaderData {
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std::unordered_map<u32, Shader::IR::Attribute> attr_map;
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std::unordered_map<u32, std::pair<Shader::IR::Attribute, u32>> attr_map;
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u32 num_attrs{0};
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};
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@ -83,15 +83,15 @@ void RingAccessElimination(const IR::Program& program, const RuntimeInfo& runtim
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const auto data = ir.BitCast<IR::F32>(IR::U32{inst.Arg(2)});
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const auto comp_ofs = runtime_info.gs_info.output_vertices * 4u;
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const auto output_size = comp_ofs * runtime_info.gs_info.out_vertex_data_size;
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const auto comp = (offset / comp_ofs) % 4;
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const auto vc_read_ofs = (((offset / comp_ofs) * comp_ofs) % output_size) * 16u;
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const auto& attr = runtime_info.gs_info.copy_data.attr_map.find(vc_read_ofs);
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ASSERT(attr != runtime_info.gs_info.copy_data.attr_map.cend());
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const auto& it = runtime_info.gs_info.copy_data.attr_map.find(vc_read_ofs);
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ASSERT(it != runtime_info.gs_info.copy_data.attr_map.cend());
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const auto& [attr, comp] = it->second;
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inst.ReplaceOpcode(IR::Opcode::SetAttribute);
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inst.ClearArgs();
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inst.SetArg(0, IR::Value{attr->second});
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inst.SetArg(0, IR::Value{attr});
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inst.SetArg(1, data);
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inst.SetArg(2, ir.Imm32(comp));
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break;
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@ -73,10 +73,10 @@ struct VertexRuntimeInfo {
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static constexpr auto GsMaxOutputStreams = 4u;
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using GsOutputPrimTypes = std::array<AmdGpu::GsOutputPrimitiveType, GsMaxOutputStreams>;
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struct GeometryRuntimeInfo {
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u32 num_invocations;
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u32 output_vertices;
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u32 in_vertex_data_size;
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u32 out_vertex_data_size;
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u32 num_invocations{};
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u32 output_vertices{};
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u32 in_vertex_data_size{};
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u32 out_vertex_data_size{};
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AmdGpu::PrimitiveType in_primitive;
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GsOutputPrimTypes out_primitive;
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CopyShaderData copy_data;
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@ -157,6 +157,10 @@ struct RuntimeInfo {
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return vs_info == other.vs_info;
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case Stage::Compute:
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return cs_info == other.cs_info;
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case Stage::Export:
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return es_info == other.es_info;
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case Stage::Geometry:
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return gs_info == other.gs_info;
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default:
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return true;
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}
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@ -322,6 +322,7 @@ bool Instance::CreateDevice() {
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.geometryShader = features.geometryShader,
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.logicOp = features.logicOp,
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.depthBiasClamp = features.depthBiasClamp,
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.fillModeNonSolid = features.fillModeNonSolid,
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.multiViewport = features.multiViewport,
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.samplerAnisotropy = features.samplerAnisotropy,
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.vertexPipelineStoresAndAtomics = features.vertexPipelineStoresAndAtomics,
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