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amdgpu: classic bitfields for T# representation (debugging experience)

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This commit is contained in:
psucien 2024-06-21 23:46:40 +02:00
parent cd1689b74b
commit 1d1d223b02
4 changed files with 54 additions and 46 deletions
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8
src/shader_recompiler/ir/passes/resource_tracking_pass.cpp
View file

@ -270,8 +270,8 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
u32 image_binding = descriptors.Add(ImageResource{
.sgpr_base = tsharp.sgpr_base,
.dword_offset = tsharp.dword_offset,
.type = image.type,
.nfmt = static_cast<AmdGpu::NumberFormat>(image.num_format.Value()),
.type = image.GetType(),
.nfmt = static_cast<AmdGpu::NumberFormat>(image.GetNumberFmt()),
.is_storage = IsImageStorageInstruction(inst),
.is_depth = bool(inst_info.is_depth),
});
@ -293,7 +293,7 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
// Now that we know the image type, adjust texture coordinate vector.
const IR::Inst* body = inst.Arg(1).InstRecursive();
const auto [coords, arg] = [&] -> std::pair<IR::Value, IR::Value> {
switch (image.type) {
switch (image.GetType()) {
case AmdGpu::ImageType::Color1D:
return {body->Arg(0), body->Arg(1)};
case AmdGpu::ImageType::Color1DArray:
@ -305,7 +305,7 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
case AmdGpu::ImageType::Cube:
return {PatchCubeCoord(ir, body->Arg(0), body->Arg(1), body->Arg(2)), body->Arg(3)};
default:
UNREACHABLE_MSG("Unknown image type {}", image.type.Value());
UNREACHABLE_MSG("Unknown image type {}", image.GetType());
}
}();
inst.SetArg(1, coords);

88
src/video_core/amdgpu/resource.h
View file

@ -108,36 +108,39 @@ constexpr std::string_view NameOf(TilingMode type) {
}
struct Image {
union {
BitField<0, 38, u64> base_address;
BitField<40, 12, u64> min_lod;
BitField<52, 6, u64> data_format;
BitField<58, 4, u64> num_format;
BitField<62, 2, u64> mtype;
};
union {
BitField<0, 14, u64> width;
BitField<14, 14, u64> height;
BitField<28, 3, u64> perf_modulation;
BitField<31, 1, u64> interlaced;
BitField<32, 3, u64> dst_sel_x;
BitField<35, 3, u64> dst_sel_y;
BitField<38, 3, u64> dst_sel_z;
BitField<41, 3, u64> dst_sel_w;
BitField<44, 4, u64> base_level;
BitField<48, 4, u64> last_level;
BitField<52, 5, u64> tiling_index;
BitField<57, 1, u64> pow2pad;
BitField<58, 1, u64> mtype2;
BitField<59, 1, u64> atc;
BitField<60, 4, ImageType> type;
};
union {
BitField<0, 13, u64> depth;
BitField<13, 14, u64> pitch;
BitField<32, 13, u64> base_array;
BitField<45, 13, u64> last_array;
};
u64 base_address : 38;
u64 mtype_l2 : 2;
u64 min_lod : 12;
u64 data_format : 6;
u64 num_format : 4;
u64 mtype : 2;
u64 width : 14;
u64 height : 14;
u64 perf_modulation : 3;
u64 interlaced : 1;
u64 dst_sel_x : 3;
u64 dst_sel_y : 3;
u64 dst_sel_z : 3;
u64 dst_sel_w : 3;
u64 base_level : 4;
u64 last_level : 4;
u64 tiling_index : 5;
u64 pow2pad : 1;
u64 mtype2 : 1;
u64 atc : 1;
u64 type : 4;
u64 depth : 13;
u64 pitch : 14;
u64 : 5;
u64 base_array : 13;
u64 last_array : 13;
u64 : 6;
u64 min_lod_warn : 12;
u64 counter_bank_id : 8;
u64 lod_hw_cnt_en : 1;
u64 : 43;
VAddr Address() const {
return base_address << 8;
@ -148,8 +151,8 @@ struct Image {
}
u32 NumLayers() const {
u32 slices = type == ImageType::Color3D ? 1 : depth.Value() + 1;
if (type == ImageType::Cube) {
u32 slices = GetType() == ImageType::Color3D ? 1 : depth + 1;
if (GetType() == ImageType::Cube) {
slices *= 6;
}
if (pow2pad) {
@ -159,33 +162,38 @@ struct Image {
}
u32 NumLevels() const {
if (type == ImageType::Color2DMsaa || type == ImageType::Color2DMsaaArray) {
if (GetType() == ImageType::Color2DMsaa || GetType() == ImageType::Color2DMsaaArray) {
return 1;
}
return last_level + 1;
}
ImageType GetType() const noexcept {
return static_cast<ImageType>(type);
}
DataFormat GetDataFmt() const noexcept {
return static_cast<DataFormat>(data_format.Value());
return static_cast<DataFormat>(data_format);
}
NumberFormat GetNumberFmt() const noexcept {
return static_cast<NumberFormat>(num_format.Value());
return static_cast<NumberFormat>(num_format);
}
[[nodiscard]] TilingMode GetTilingMode() const {
return static_cast<TilingMode>(tiling_index.Value());
TilingMode GetTilingMode() const {
return static_cast<TilingMode>(tiling_index);
}
[[nodiscard]] bool IsTiled() const {
bool IsTiled() const {
return GetTilingMode() != TilingMode::Display_Linear;
}
[[nodiscard]] size_t GetSizeAligned() const {
size_t GetSizeAligned() const {
// TODO: Derive this properly from tiling params
return (width + 1) * (height + 1) * NumComponents(GetDataFmt());
return Pitch() * (height + 1) * NumComponents(GetDataFmt());
}
};
static_assert(sizeof(Image) == 32); // 256bits
// 8.2.7. Image Sampler [RDNA 2 Instruction Set Architecture]
enum class ClampMode : u64 {

2
src/video_core/texture_cache/image.cpp
View file

@ -164,7 +164,7 @@ ImageInfo::ImageInfo(const AmdGpu::Image& image) noexcept {
is_tiled = image.IsTiled();
tiling_mode = image.GetTilingMode();
pixel_format = LiverpoolToVK::SurfaceFormat(image.GetDataFmt(), image.GetNumberFmt());
type = ConvertImageType(image.type);
type = ConvertImageType(image.GetType());
size.width = image.width + 1;
size.height = image.height + 1;
size.depth = 1;

2
src/video_core/texture_cache/image_view.cpp
View file

@ -48,7 +48,7 @@ vk::ComponentSwizzle ConvertComponentSwizzle(u32 dst_sel) {
ImageViewInfo::ImageViewInfo(const AmdGpu::Image& image, bool is_storage) noexcept
: is_storage{is_storage} {
type = ConvertImageViewType(image.type);
type = ConvertImageViewType(image.GetType());
format = Vulkan::LiverpoolToVK::SurfaceFormat(image.GetDataFmt(), image.GetNumberFmt());
range.base.level = 0;
range.base.layer = 0;