mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-04-21 12:04:45 +00:00
x64 fixes
This commit is contained in:
Lander Gallastegi
parent
62b7dc2300
commit
46e2cbd2ab
8 changed files with 88 additions and 117 deletions
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@ -107,7 +107,8 @@ void EmitInst(EmitContext& ctx, IR::Inst* inst) {
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switch (inst->GetOpcode()) {
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#define OPCODE(name, result_type, ...) \
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case IR::Opcode::name: \
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Invoke<&Emit##name, IR::Type::result_type != IR::Type::Void>(ctx, inst);
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Invoke<&Emit##name, IR::Type::result_type != IR::Type::Void>(ctx, inst); \
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return;
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#include "shader_recompiler/ir/opcodes.inc"
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#undef OPCODE
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}
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@ -138,6 +139,8 @@ void Traverse(EmitContext& ctx, const IR::Program& program) {
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IR::Block* block = node.data.block;
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c.L(ctx.BlockLabel(block));
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for (IR::Inst& inst : *block) {
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ctx.ResetTempRegs();
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EmitInst(ctx, &inst);
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}
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const auto& phi_assignments = ctx.PhiAssignments(block);
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if (phi_assignments) {
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@ -14,7 +14,7 @@ void EmitGetUserData(EmitContext& ctx, const Operands& dest, IR::ScalarReg reg)
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const u32 offset = static_cast<u32>(reg) << 2;
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Reg& tmp = ctx.TempGPReg();
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ctx.Code().lea(tmp, ptr[ctx.UserData() + offset]);
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MovGP( ctx, dest[0], ptr[tmp]);
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MovGP( ctx, dest[0], dword[tmp]);
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}
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void EmitSetUserData(EmitContext& ctx, const Operands& offset, const Operands& value) {
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@ -22,7 +22,7 @@ void EmitSetUserData(EmitContext& ctx, const Operands& offset, const Operands& v
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MovGP(ctx, tmp, offset[0]);
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ctx.Code().shl(tmp, 2);
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ctx.Code().lea(tmp, ptr[ctx.UserData() + tmp]);
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MovGP(ctx, ptr[tmp], value[0]);
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MovGP(ctx, dword[tmp], value[0]);
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}
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void EmitGetThreadBitScalarReg(EmitContext& ctx) {
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@ -65,9 +65,9 @@ void EmitReadConst(EmitContext& ctx, const Operands& dest, const Operands& base,
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if (offset[0].isMEM()) {
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ctx.Code().add(tmp, offset[0]);
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} else {
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ctx.Code().lea(tmp, ptr[tmp + offset[0].getReg()]);
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ctx.Code().lea(tmp, ptr[tmp + offset[0].getReg().cvt64()]);
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}
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MovGP(ctx, dest[0], ptr[tmp]);
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MovGP(ctx, dest[0], dword[tmp]);
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}
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void EmitReadConstBuffer(EmitContext& ctx) {
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@ -328,8 +328,8 @@ void EmitIAdd64(EmitContext& ctx, const Operands& dest, const Operands& op1, con
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void EmitIAddCary32(EmitContext& ctx, const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitISub32(EmitContext& ctx, const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitISub64(EmitContext& ctx, const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitSMulExt(EmitContext& ctx,const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitUMulExt(EmitContext& ctx,const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitSMulExt(EmitContext& ctx);
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void EmitUMulExt(EmitContext& ctx);
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void EmitIMul32(EmitContext& ctx, const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitIMul64(EmitContext& ctx, const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitSDiv32(EmitContext& ctx, const Operands& dest, const Operands& op1, const Operands& op2);
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@ -350,9 +350,9 @@ void EmitBitwiseAnd64(EmitContext& ctx, const Operands& dest, const Operands& op
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void EmitBitwiseOr32(EmitContext& ctx, const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitBitwiseOr64(EmitContext& ctx, const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitBitwiseXor32(EmitContext& ctx, const Operands& dest, const Operands& op1, const Operands& op2);
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void EmitBitFieldInsert(EmitContext& ctx, const Operands& dest, const Operands& base, const Operands& insert, const Operands& offset, const Operands& count);
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void EmitBitFieldSExtract(EmitContext& ctx, const Operands& dest, const Operands& base, const Operands& offset, const Operands& count);
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void EmitBitFieldUExtract(EmitContext& ctx, const Operands& dest, const Operands& base, const Operands& offset, const Operands& count);
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void EmitBitFieldInsert(EmitContext& ctx);
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void EmitBitFieldSExtract(EmitContext& ctx);
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void EmitBitFieldUExtract(EmitContext& ctx);
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void EmitBitReverse32(EmitContext& ctx);
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void EmitBitCount32(EmitContext& ctx);
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void EmitBitCount64(EmitContext& ctx);
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@ -125,7 +125,7 @@ Operands EmitContext::Def(const IR::Value& value) {
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code.mov(operands.back(), std::bit_cast<u64>(value.Patch()));
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break;
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default:
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UNREACHABLE_MSG("Unsupported value type: %s", IR::NameOf(value.Type()));
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UNREACHABLE_MSG("Unsupported value type: {}", IR::NameOf(value.Type()));
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break;
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}
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return operands;
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@ -173,17 +173,17 @@ void EmitContext::SpillInst(RegAllocContext& ctx, const ActiveInstInterval& inte
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current_sp += ctx.free_stack_slots.back();
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ctx.free_stack_slots.pop_back();
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}
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switch (GetRegBytesOfType(inst->Type())) {
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case 8:
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switch (GetRegBytesOfType(IR::Value(inst))) {
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case 1:
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return byte[r11 + current_sp];
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case 16:
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case 2:
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return word[r11 + current_sp];
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case 32:
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case 4:
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return dword[r11 + current_sp];
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case 64:
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case 8:
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return qword[r11 + current_sp];
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default:
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UNREACHABLE_MSG("Unsupported register size: %zu", GetRegBytesOfType(inst->Type()));
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UNREACHABLE_MSG("Unsupported register size: {}", GetRegBytesOfType(inst));
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return {};
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}
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};
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@ -197,7 +197,7 @@ void EmitContext::SpillInst(RegAllocContext& ctx, const ActiveInstInterval& inte
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Operands& operands = inst_to_operands[spill_candidate->inst];
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Reg reg = operands[spill_candidate->component].getReg();
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inst_to_operands[interval.inst][interval.component] =
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reg.isXMM() ? reg : ResizeRegToType(reg, interval.inst->Type());
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reg.isXMM() ? reg : ResizeRegToType(reg, interval.inst);
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operands[spill_candidate->component] = get_operand(spill_candidate->inst);
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ctx.active_spill_intervals.push_back(*spill_candidate);
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*spill_candidate = interval;
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@ -252,8 +252,8 @@ void EmitContext::AllocateRegisters() {
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const std::array<Reg64, 6> initial_gp_inst_regs = {rcx, rdx, rsi, r8, r9, r10};
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const std::array<Xmm, 7> initial_xmm_inst_regs = {xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6};
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const std::array<Reg64, 6> initial_gp_temp_regs = {rax, rbx, r12, r13, r14, r15};
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const std::array<Xmm, 10> initial_xmm_temp_regs = {xmm7, xmm7, xmm8, xmm9, xmm10,
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xmm11, xmm12, xmm13, xmm14, xmm15};
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const std::array<Xmm, 9> initial_xmm_temp_regs = {xmm7, xmm8, xmm9, xmm10, xmm11,
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xmm12, xmm13, xmm14, xmm15};
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boost::container::small_vector<InstInterval, 64> intervals;
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FlatInstList insts;
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@ -274,10 +274,10 @@ void EmitContext::AllocateRegisters() {
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std::sort(intervals.begin(), intervals.end(),
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[](const InstInterval& a, const InstInterval& b) { return a.start < b.start; });
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RegAllocContext ctx;
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ctx.free_gp_regs.insert(ctx.free_gp_regs.end(), initial_gp_temp_regs.begin(),
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initial_gp_temp_regs.end());
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ctx.free_xmm_regs.insert(ctx.free_xmm_regs.end(), initial_xmm_temp_regs.begin(),
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initial_xmm_temp_regs.end());
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ctx.free_gp_regs.insert(ctx.free_gp_regs.end(), initial_gp_inst_regs.begin(),
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initial_gp_inst_regs.end());
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ctx.free_xmm_regs.insert(ctx.free_xmm_regs.end(), initial_xmm_inst_regs.begin(),
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initial_xmm_inst_regs.end());
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boost::container::static_vector<Reg64, 6> unused_gp_inst_regs;
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boost::container::static_vector<Xmm, 7> unused_xmm_inst_regs;
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unused_gp_inst_regs.insert(unused_gp_inst_regs.end(), ctx.free_gp_regs.begin(),
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@ -287,7 +287,7 @@ void EmitContext::AllocateRegisters() {
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for (const InstInterval& interval : intervals) {
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// Free old interval resources
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for (auto it = ctx.active_gp_intervals.begin(); it != ctx.active_gp_intervals.end();) {
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if (it->end <= interval.start) {
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if (it->end < interval.start) {
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Reg64 reg = inst_to_operands[it->inst][it->component].getReg().cvt64();
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ctx.free_gp_regs.push_back(reg);
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it = ctx.active_gp_intervals.erase(it);
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@ -296,7 +296,7 @@ void EmitContext::AllocateRegisters() {
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}
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}
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for (auto it = ctx.active_xmm_intervals.begin(); it != ctx.active_xmm_intervals.end();) {
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if (it->end <= interval.start) {
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if (it->end < interval.start) {
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Xmm reg = inst_to_operands[it->inst][it->component].getReg().cvt128();
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ctx.free_xmm_regs.push_back(reg);
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it = ctx.active_xmm_intervals.erase(it);
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@ -306,7 +306,7 @@ void EmitContext::AllocateRegisters() {
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}
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for (auto it = ctx.active_spill_intervals.begin();
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it != ctx.active_spill_intervals.end();) {
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if (it->end <= interval.start) {
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if (it->end < interval.start) {
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const Address& addr = inst_to_operands[it->inst][it->component].getAddress();
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ctx.free_stack_slots.push_back(addr.getDisp());
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it = ctx.active_spill_intervals.erase(it);
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@ -314,15 +314,17 @@ void EmitContext::AllocateRegisters() {
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++it;
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}
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}
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u8 num_components = GetNumComponentsOfType(interval.inst->Type());
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bool is_floating = IsFloatingType(interval.inst->Type());
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u8 num_components = GetNumComponentsOfType(interval.inst);
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bool is_floating = IsFloatingType(interval.inst);
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auto& operands = inst_to_operands[interval.inst];
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operands.resize(num_components);
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if (is_floating) {
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for (size_t i = 0; i < num_components; ++i) {
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ActiveInstInterval active(interval, i);
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if (!ctx.free_xmm_regs.empty()) {
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Xmm& reg = ctx.free_xmm_regs.back();
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ctx.free_xmm_regs.pop_back();
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inst_to_operands[active.inst][active.component] = reg;
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operands[active.component] = reg;
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unused_xmm_inst_regs.erase(
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std::remove(unused_xmm_inst_regs.begin(), unused_xmm_inst_regs.end(), reg),
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unused_xmm_inst_regs.end());
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@ -337,8 +339,7 @@ void EmitContext::AllocateRegisters() {
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if (!ctx.free_gp_regs.empty()) {
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Reg64& reg = ctx.free_gp_regs.back();
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ctx.free_gp_regs.pop_back();
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inst_to_operands[active.inst][active.component] =
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ResizeRegToType(reg, active.inst->Type());
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operands[active.component] = ResizeRegToType(reg, active.inst);
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unused_gp_inst_regs.erase(
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std::remove(unused_gp_inst_regs.begin(), unused_gp_inst_regs.end(), reg),
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unused_gp_inst_regs.end());
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@ -354,10 +355,10 @@ void EmitContext::AllocateRegisters() {
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unused_xmm_inst_regs.end());
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num_scratch_gp_regs = unused_gp_inst_regs.size() + 1; // rax is scratch
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num_scratch_xmm_regs = unused_xmm_inst_regs.size() + 1; // xmm7 is scratch
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temp_gp_regs.insert(temp_gp_regs.end(), initial_gp_inst_regs.begin(),
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initial_gp_inst_regs.end());
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temp_xmm_regs.insert(temp_xmm_regs.end(), initial_xmm_inst_regs.begin(),
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initial_xmm_inst_regs.end());
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temp_gp_regs.insert(temp_gp_regs.end(), initial_gp_temp_regs.begin(),
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initial_gp_temp_regs.end());
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temp_xmm_regs.insert(temp_xmm_regs.end(), initial_xmm_temp_regs.begin(),
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initial_xmm_temp_regs.end());
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}
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} // namespace Shader::Backend::X64
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@ -54,7 +54,7 @@ public:
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void PopTempXmmReg();
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void ResetTempRegs();
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[[nodiscard]] const Xbyak::Reg64& UserData() const {return Xbyak::util::r11;}
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[[nodiscard]] const Xbyak::Reg64& UserData() const {return Xbyak::util::rdi;}
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[[nodiscard]] const Operands& Def(IR::Inst* inst);
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[[nodiscard]] Operands Def(const IR::Value& value);
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@ -8,65 +8,15 @@ using namespace Xbyak::util;
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namespace Shader::Backend::X64 {
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bool IsFloatingType(IR::Type type) {
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bool IsFloatingType(const IR::Value& value) {
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// We store F16 on general purpose registers since we don't do
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// arithmetic on them
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IR::Type type = value.Type();
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return type == IR::Type::F32 || type == IR::Type::F64;
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}
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bool IsConditionalOpcode(IR::Opcode opcode) {
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switch (opcode) {
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case IR::Opcode::FPOrdEqual32:
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case IR::Opcode::FPOrdEqual64:
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case IR::Opcode::FPUnordEqual32:
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case IR::Opcode::FPUnordEqual64:
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case IR::Opcode::FPOrdNotEqual32:
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case IR::Opcode::FPOrdNotEqual64:
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case IR::Opcode::FPUnordNotEqual32:
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case IR::Opcode::FPUnordNotEqual64:
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case IR::Opcode::FPOrdLessThan32:
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case IR::Opcode::FPOrdLessThan64:
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case IR::Opcode::FPUnordLessThan32:
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case IR::Opcode::FPUnordLessThan64:
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case IR::Opcode::FPOrdGreaterThan32:
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case IR::Opcode::FPOrdGreaterThan64:
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case IR::Opcode::FPUnordGreaterThan32:
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case IR::Opcode::FPUnordGreaterThan64:
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case IR::Opcode::FPOrdLessThanEqual32:
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case IR::Opcode::FPOrdLessThanEqual64:
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case IR::Opcode::FPUnordLessThanEqual32:
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case IR::Opcode::FPUnordLessThanEqual64:
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case IR::Opcode::FPOrdGreaterThanEqual32:
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case IR::Opcode::FPOrdGreaterThanEqual64:
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case IR::Opcode::FPUnordGreaterThanEqual32:
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case IR::Opcode::FPUnordGreaterThanEqual64:
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case IR::Opcode::FPIsNan32:
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case IR::Opcode::FPIsNan64:
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case IR::Opcode::FPIsInf32:
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case IR::Opcode::FPIsInf64:
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case IR::Opcode::FPCmpClass32:
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case IR::Opcode::SLessThan32:
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case IR::Opcode::SLessThan64:
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case IR::Opcode::ULessThan32:
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case IR::Opcode::ULessThan64:
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case IR::Opcode::IEqual32:
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case IR::Opcode::IEqual64:
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case IR::Opcode::SLessThanEqual:
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case IR::Opcode::ULessThanEqual:
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case IR::Opcode::SGreaterThan:
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case IR::Opcode::UGreaterThan:
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case IR::Opcode::INotEqual32:
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case IR::Opcode::INotEqual64:
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case IR::Opcode::SGreaterThanEqual:
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case IR::Opcode::UGreaterThanEqual:
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return true;
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default:
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return false;
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}
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}
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size_t GetRegBytesOfType(IR::Type type) {
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switch (type) {
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size_t GetRegBytesOfType(const IR::Value& value) {
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switch (value.Type()) {
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case IR::Type::U1:
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case IR::Type::U8:
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return 1;
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@ -98,12 +48,12 @@ size_t GetRegBytesOfType(IR::Type type) {
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default:
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break;
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}
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UNREACHABLE_MSG("Unsupported type %s", IR::NameOf(type));
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UNREACHABLE_MSG("Unsupported type {}", IR::NameOf(value.Type()));
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return 0;
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}
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u8 GetNumComponentsOfType(IR::Type type) {
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switch (type) {
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u8 GetNumComponentsOfType(const IR::Value& value) {
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switch (value.Type()) {
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case IR::Type::U1:
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case IR::Type::U8:
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case IR::Type::U16:
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@ -135,13 +85,13 @@ u8 GetNumComponentsOfType(IR::Type type) {
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default:
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break;
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}
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UNREACHABLE_MSG("Unsupported type %s", IR::NameOf(type));
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UNREACHABLE_MSG("Unsupported type {}", IR::NameOf(value.Type()));
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return 0;
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}
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Reg ResizeRegToType(const Reg& reg, IR::Type type) {
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Reg ResizeRegToType(const Reg& reg, const IR::Value& value) {
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ASSERT(reg.getKind() == Operand::Kind::REG);
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switch (GetRegBytesOfType(type)) {
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switch (GetRegBytesOfType(value)) {
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case 1:
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return reg.cvt8();
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case 2:
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@ -153,7 +103,7 @@ Reg ResizeRegToType(const Reg& reg, IR::Type type) {
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default:
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break;
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}
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UNREACHABLE_MSG("Unsupported type %s", IR::NameOf(type));
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UNREACHABLE_MSG("Unsupported type {}", IR::NameOf(value.Type()));
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return reg;
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}
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@ -173,7 +123,7 @@ void MovFloat(EmitContext& ctx, const Xbyak::Operand& dst, const Xbyak::Operand&
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} else if (src.isXMM() && dst.isXMM()) {
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c.movaps(dst.getReg().cvt128(), src.getReg().cvt128());
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} else {
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UNREACHABLE_MSG("Unsupported mov float %s %s", src.toString(), dst.toString());
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UNREACHABLE_MSG("Unsupported mov float {} {}", src.toString(), dst.toString());
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}
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}
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||||
|
||||
|
|
@ -193,7 +143,7 @@ void MovDouble(EmitContext& ctx, const Xbyak::Operand& dst, const Xbyak::Operand
|
|||
} else if (src.isXMM() && dst.isXMM()) {
|
||||
c.movapd(dst.getReg().cvt128(), src.getReg().cvt128());
|
||||
} else {
|
||||
UNREACHABLE_MSG("Unsupported mov double %s %s", src.toString(), dst.toString());
|
||||
UNREACHABLE_MSG("Unsupported mov double {} {}", src.toString(), dst.toString());
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -202,26 +152,27 @@ void MovGP(EmitContext& ctx, const Xbyak::Operand& dst, const Xbyak::Operand& sr
|
|||
if (src == dst) {
|
||||
return;
|
||||
}
|
||||
Reg tmp = (src.isMEM() && dst.isMEM()) ? ctx.TempGPReg(false).changeBit(dst.getBit()) : dst.getReg();
|
||||
if (src.getBit() == dst.getBit()) {
|
||||
c.mov(tmp, src);
|
||||
} else if (src.getBit() < dst.getBit()) {
|
||||
Reg tmp = dst.isMEM() ? ctx.TempGPReg(false).changeBit(dst.getBit()) : dst.getReg();
|
||||
if (src.getBit() < dst.getBit() && !src.isBit(32)) {
|
||||
c.movzx(tmp, src);
|
||||
} else {
|
||||
} else if (src.getBit() > dst.getBit()) {
|
||||
Operand src_tmp = src;
|
||||
src_tmp.setBit(dst.getBit());
|
||||
c.mov(tmp, src_tmp);
|
||||
} else {
|
||||
c.mov(tmp, src);
|
||||
}
|
||||
if (src.isMEM() && dst.isMEM()) {
|
||||
if (dst.isMEM()) {
|
||||
c.mov(dst, tmp);
|
||||
}
|
||||
}
|
||||
|
||||
void MovValue(EmitContext& ctx, const Operands& dst, const IR::Value& src) {
|
||||
if (!src.IsImmediate()) {
|
||||
const Operands& src_op = ctx.Def(src);
|
||||
if (IsFloatingType(src.Type())) {
|
||||
switch (GetRegBytesOfType(src.Type())) {
|
||||
IR::Inst* src_inst = src.InstRecursive();
|
||||
const Operands& src_op = ctx.Def(src_inst);
|
||||
if (IsFloatingType(src)) {
|
||||
switch (GetRegBytesOfType(src)) {
|
||||
case 32:
|
||||
for (size_t i = 0; i < src_op.size(); i++) {
|
||||
MovFloat(ctx, dst[i], src_op[i]);
|
||||
|
|
@ -233,7 +184,7 @@ void MovValue(EmitContext& ctx, const Operands& dst, const IR::Value& src) {
|
|||
}
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE_MSG("Unsupported type %s", IR::NameOf(src.Type()));
|
||||
UNREACHABLE_MSG("Unsupported type {}", IR::NameOf(src.Type()));
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
|
|
@ -288,7 +239,7 @@ void MovValue(EmitContext& ctx, const Operands& dst, const IR::Value& src) {
|
|||
c.mov(is_mem ? tmp : dst[0], std::bit_cast<u64>(src.Patch()));
|
||||
break;
|
||||
default:
|
||||
UNREACHABLE_MSG("Unsupported type %s", IR::NameOf(src.Type()));
|
||||
UNREACHABLE_MSG("Unsupported type {}", IR::NameOf(src.Type()));
|
||||
break;
|
||||
}
|
||||
if (is_mem) {
|
||||
|
|
|
|||
|
|
@ -10,11 +10,10 @@
|
|||
|
||||
namespace Shader::Backend::X64 {
|
||||
|
||||
bool IsFloatingType(IR::Type type);
|
||||
bool IsConditionalOpcode(IR::Opcode opcode);
|
||||
size_t GetRegBytesOfType(IR::Type type);
|
||||
u8 GetNumComponentsOfType(IR::Type type);
|
||||
Xbyak::Reg ResizeRegToType(const Xbyak::Reg& reg, IR::Type type);
|
||||
bool IsFloatingType(const IR::Value& value);
|
||||
size_t GetRegBytesOfType(const IR::Value& value);
|
||||
u8 GetNumComponentsOfType(const IR::Value& value);
|
||||
Xbyak::Reg ResizeRegToType(const Xbyak::Reg& reg, const IR::Value& value);
|
||||
void MovFloat(EmitContext& ctx, const Xbyak::Operand& dst, const Xbyak::Operand& src);
|
||||
void MovDouble(EmitContext& ctx, const Xbyak::Operand& dst, const Xbyak::Operand& src);
|
||||
void MovGP(EmitContext& ctx, const Xbyak::Operand& dst, const Xbyak::Operand& src);
|
||||
|
|
@ -22,4 +21,20 @@ void MovValue(EmitContext& ctx, const Operands& dst, const IR::Value& src);
|
|||
void EmitInlineF16ToF32(EmitContext& ctx, const Xbyak::Operand& dest, const Xbyak::Operand& src);
|
||||
void EmitInlineF32ToF16(EmitContext& ctx, const Xbyak::Operand& dest, const Xbyak::Operand& src);
|
||||
|
||||
inline bool IsFloatingType(IR::Inst* inst) {
|
||||
return IsFloatingType(IR::Value(inst));
|
||||
}
|
||||
|
||||
inline size_t GetRegBytesOfType(IR::Inst* inst) {
|
||||
return GetRegBytesOfType(IR::Value(inst));
|
||||
}
|
||||
|
||||
inline u8 GetNumComponentsOfType(IR::Inst* inst) {
|
||||
return GetNumComponentsOfType(IR::Value(inst));
|
||||
}
|
||||
|
||||
inline Xbyak::Reg ResizeRegToType(const Xbyak::Reg& reg, IR::Inst* inst) {
|
||||
return ResizeRegToType(reg, IR::Value(inst));
|
||||
}
|
||||
|
||||
} // namespace Shader::Backend::X64
|
||||
|
|
@ -214,7 +214,8 @@ static void GenerateSrtProgram(IR::Program& program, PassInfo& pass_info, Pools&
|
|||
ASSERT(pass_info.dst_off_dw == info.srt_info.flattened_bufsize_dw);
|
||||
|
||||
if (!pass_info.all_readconsts.empty()) {
|
||||
GenerateSrtReadConstsSubProgram(program, pass_info, pools);
|
||||
IR::Program sub_program = GenerateSrtReadConstsSubProgram(program, pass_info, pools);
|
||||
Backend::X64::EmitX64(sub_program, c);
|
||||
}
|
||||
|
||||
info.srt_info.flattened_bufsize_dw = pass_info.dst_off_dw;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue