mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-04-21 03:54:45 +00:00
shader_recompiler: rewrite GetSrc api to allow compile-time check of types
This commit is contained in:
Vinicius Rangel
parent
501bc704bf
commit
523fc24fb1
7 changed files with 277 additions and 211 deletions
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@ -110,17 +110,17 @@ void Translator::S_BARRIER() {
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void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) {
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ASSERT(info.stage != Stage::Compute);
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SetDst(inst.dst[0], GetSrc(inst.src[0]));
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SetDst(inst.dst[0], GetSrc<IR::U32>(inst.src[0]));
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}
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void Translator::V_READLANE_B32(const GcnInst& inst) {
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ASSERT(info.stage != Stage::Compute);
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SetDst(inst.dst[0], GetSrc(inst.src[0]));
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SetDst(inst.dst[0], GetSrc<IR::U32>(inst.src[0]));
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}
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void Translator::V_WRITELANE_B32(const GcnInst& inst) {
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ASSERT(info.stage != Stage::Compute);
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SetDst(inst.dst[0], GetSrc(inst.src[0]));
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SetDst(inst.dst[0], GetSrc<IR::U32>(inst.src[0]));
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}
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} // namespace Shader::Gcn
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@ -110,25 +110,25 @@ void Translator::S_MOVK(const GcnInst& inst) {
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void Translator::S_ADDK_I32(const GcnInst& inst) {
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const s32 simm16 = inst.control.sopk.simm;
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SetDst(inst.dst[0], ir.IAdd(GetSrc(inst.dst[0], true), ir.Imm32(simm16)));
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SetDst(inst.dst[0], ir.IAdd(GetSrc<IR::U32>(inst.dst[0]), ir.Imm32(simm16)));
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}
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void Translator::S_MULK_I32(const GcnInst& inst) {
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const s32 simm16 = inst.control.sopk.simm;
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SetDst(inst.dst[0], ir.IMul(GetSrc(inst.dst[0], true), ir.Imm32(simm16)));
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SetDst(inst.dst[0], ir.IMul(GetSrc<IR::U32>(inst.dst[0]), ir.Imm32(simm16)));
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}
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void Translator::S_MOV(const GcnInst& inst) {
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SetDst(inst.dst[0], GetSrc(inst.src[0]));
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SetDst(inst.dst[0], GetSrc<IR::U32>(inst.src[0]));
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}
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void Translator::S_MUL_I32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.IMul(GetSrc(inst.src[0], true), GetSrc(inst.src[1], true)));
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SetDst(inst.dst[0], ir.IMul(GetSrc<IR::U32>(inst.src[0]), GetSrc<IR::U32>(inst.src[1])));
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}
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void Translator::S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst) {
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const IR::U32 lhs = GetSrc(inst.src[0], true);
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const IR::U32 rhs = GetSrc(inst.src[1], true);
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const IR::U32 lhs = GetSrc(inst.src[0]);
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const IR::U32 rhs = GetSrc(inst.src[1]);
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const IR::U1 result = [&] {
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switch (cond) {
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case ConditionOp::EQ:
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@ -288,47 +288,47 @@ void Translator::S_AND_B64(NegateMode negate, const GcnInst& inst) {
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}
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void Translator::S_ADD_I32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], ir.IAdd(src0, src1));
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// TODO: Overflow flag
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}
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void Translator::S_AND_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 result{ir.BitwiseAnd(src0, src1)};
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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}
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void Translator::S_ASHR_I32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 result{ir.ShiftRightArithmetic(src0, src1)};
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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}
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void Translator::S_OR_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 result{ir.BitwiseOr(src0, src1)};
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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}
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void Translator::S_LSHR_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 result{ir.ShiftRightLogical(src0, src1)};
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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}
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void Translator::S_CSELECT_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], IR::U32{ir.Select(ir.GetScc(), src0, src1)});
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}
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@ -363,8 +363,8 @@ void Translator::S_CSELECT_B64(const GcnInst& inst) {
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}
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void Translator::S_BFE_U32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 offset{ir.BitwiseAnd(src1, ir.Imm32(0x1F))};
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const IR::U32 count{ir.BitFieldExtract(src1, ir.Imm32(16), ir.Imm32(7))};
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const IR::U32 result{ir.BitFieldExtract(src0, offset, count)};
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@ -373,16 +373,16 @@ void Translator::S_BFE_U32(const GcnInst& inst) {
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}
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void Translator::S_LSHL_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 result = ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F)));
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
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}
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void Translator::S_BFM_B32(const GcnInst& inst) {
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const IR::U32 src0{ir.BitwiseAnd(GetSrc(inst.src[0], true), ir.Imm32(0x1F))};
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const IR::U32 src1{ir.BitwiseAnd(GetSrc(inst.src[1], true), ir.Imm32(0x1F))};
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const IR::U32 src0{ir.BitwiseAnd(GetSrc(inst.src[0]), ir.Imm32(0x1F))};
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const IR::U32 src1{ir.BitwiseAnd(GetSrc(inst.src[1]), ir.Imm32(0x1F))};
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const IR::U32 mask{ir.ISub(ir.ShiftLeftLogical(ir.Imm32(1u), src0), ir.Imm32(1))};
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SetDst(inst.dst[0], ir.ShiftLeftLogical(mask, src1));
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}
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@ -420,16 +420,16 @@ void Translator::S_BREV_B32(const GcnInst& inst) {
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}
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void Translator::S_ADD_U32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], ir.IAdd(src0, src1));
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// TODO: Carry out
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ir.SetScc(ir.Imm1(false));
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}
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void Translator::S_SUB_U32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], ir.ISub(src0, src1));
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// TODO: Carry out
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ir.SetScc(ir.Imm1(false));
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@ -442,22 +442,22 @@ void Translator::S_GETPC_B64(u32 pc, const GcnInst& inst) {
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}
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void Translator::S_ADDC_U32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], ir.IAdd(ir.IAdd(src0, src1), ir.GetSccLo()));
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}
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void Translator::S_MAX_U32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 result = ir.UMax(src0, src1);
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.IEqual(result, src0));
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}
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void Translator::S_MIN_U32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0], true)};
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const IR::U32 src1{GetSrc(inst.src[1], true)};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 result = ir.UMin(src0, src1);
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SetDst(inst.dst[0], result);
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ir.SetScc(ir.IEqual(result, src0));
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@ -73,10 +73,12 @@ void Translator::EmitPrologue() {
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}
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}
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template <>
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IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool integer) {
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IR::U32F32 Translator::GetSrcRaw(const InstOperand& operand, bool integer) {
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IR::U32F32 value{};
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ASSERT(operand.type != ScalarType::Float64 && operand.type != ScalarType::Uint64 &&
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operand.type != ScalarType::Sint64);
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const bool is_float = operand.type == ScalarType::Float32 && !integer;
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switch (operand.field) {
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@ -180,26 +182,18 @@ IR::U32F32 Translator::GetSrc(const InstOperand& operand, bool integer) {
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return value;
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}
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template <>
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IR::U32 Translator::GetSrc(const InstOperand& operand, bool) {
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return GetSrc<IR::U32F32>(operand, true);
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}
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template <>
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IR::F32 Translator::GetSrc(const InstOperand& operand, bool integer) {
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return GetSrc<IR::U32F32>(operand, integer);
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}
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template <>
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IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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IR::U64F64 Translator::GetSrcRaw64(const InstOperand& operand, bool integer) {
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IR::Value value_hi{};
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IR::Value value_lo{};
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ASSERT(operand.type == ScalarType::Float64 || operand.type == ScalarType::Uint64 ||
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operand.type == ScalarType::Sint64);
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bool immediate = false;
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const bool is_float = operand.type == ScalarType::Float64 || force_flt;
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const bool is_float = operand.type == ScalarType::Float64 && !integer;
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switch (operand.field) {
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case OperandField::ScalarGPR:
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if (is_float) {
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if (!integer) {
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value_lo = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code));
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value_hi = ir.GetScalarReg<IR::F32>(IR::ScalarReg(operand.code + 1));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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@ -210,7 +204,7 @@ IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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}
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break;
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case OperandField::VectorGPR:
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if (is_float) {
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if (integer) {
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value_lo = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code));
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value_hi = ir.GetVectorReg<IR::F32>(IR::VectorReg(operand.code + 1));
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} else if (operand.type == ScalarType::Uint64 || operand.type == ScalarType::Sint64) {
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@ -222,25 +216,25 @@ IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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break;
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case OperandField::ConstZero:
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immediate = true;
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if (force_flt) {
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if (is_float) {
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value_lo = ir.Imm64(0.0);
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} else {
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value_lo = ir.Imm64(u64(0U));
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}
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break;
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case OperandField::SignedConstIntPos:
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ASSERT(!force_flt);
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ASSERT(!is_float);
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immediate = true;
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value_lo = ir.Imm64(s64(operand.code) - SignedConstIntPosMin + 1);
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break;
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case OperandField::SignedConstIntNeg:
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ASSERT(!force_flt);
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ASSERT(!is_float);
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immediate = true;
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value_lo = ir.Imm64(-s64(operand.code) + SignedConstIntNegMin - 1);
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break;
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case OperandField::LiteralConst:
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immediate = true;
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if (force_flt) {
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if (is_float) {
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UNREACHABLE(); // There is a literal double?
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} else {
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value_lo = ir.Imm64(u64(operand.code));
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@ -248,7 +242,7 @@ IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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break;
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case OperandField::ConstFloatPos_1_0:
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immediate = true;
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if (force_flt) {
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if (is_float) {
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value_lo = ir.Imm64(1.0);
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} else {
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value_lo = ir.Imm64(std::bit_cast<u64>(f64(1.0)));
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@ -303,7 +297,7 @@ IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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value = ir.PackUint2x32(packed);
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}
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if (is_float) {
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if (!integer) {
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if (operand.input_modifier.abs) {
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value = ir.FPAbs(IR::F32F64(value));
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}
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@ -315,12 +309,69 @@ IR::U64F64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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}
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template <>
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IR::U64 Translator::GetSrc64(const InstOperand& operand, bool force_flt) {
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return GetSrc64<IR::U64F64>(operand, force_flt);
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Translator::SrcAuto Translator::GetSrc<Translator::SrcAuto>(const InstOperand& operand) {
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return SrcAuto{
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*this,
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operand,
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};
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}
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template <>
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IR::F64 Translator::GetSrc64(const InstOperand& operand, bool) {
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return GetSrc64<IR::U64F64>(operand, true);
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IR::U32F32 Translator::GetSrc(const InstOperand& operand) {
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return GetSrcRaw(operand, false);
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}
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template <>
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IR::U32 Translator::GetSrc(const InstOperand& operand) {
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return GetSrcRaw(operand, true);
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}
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template <>
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IR::F32 Translator::GetSrc(const InstOperand& operand) {
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return GetSrcRaw(operand, false);
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}
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template <>
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IR::U64F64 Translator::GetSrc(const InstOperand& operand) {
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return GetSrcRaw64(operand, false);
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}
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template <>
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IR::U64 Translator::GetSrc(const InstOperand& operand) {
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return GetSrcRaw64(operand, true);
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}
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template <>
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IR::F64 Translator::GetSrc(const InstOperand& operand) {
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return GetSrcRaw64(operand, false);
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}
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Translator::SrcAuto::operator IR::U32F32() const {
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return translator.GetSrc<IR::U32F32>(operand);
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}
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Translator::SrcAuto::operator IR::Value() const {
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return IR::Value{translator.GetSrc<IR::U32F32>(operand)};
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}
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Translator::SrcAuto::operator IR::U32() const {
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return translator.GetSrc<IR::U32>(operand);
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}
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Translator::SrcAuto::operator IR::F32() const {
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return translator.GetSrc<IR::F32>(operand);
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}
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Translator::SrcAuto::operator IR::U64F64() const {
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return translator.GetSrc<IR::U64F64>(operand);
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}
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||||
|
||||
Translator::SrcAuto::operator IR::U64() const {
|
||||
return translator.GetSrc<IR::U64>(operand);
|
||||
}
|
||||
|
||||
Translator::SrcAuto::operator IR::F64() const {
|
||||
return translator.GetSrc<IR::F64>(operand);
|
||||
}
|
||||
|
||||
void Translator::SetDst(const InstOperand& operand, const IR::U32F32& value) {
|
||||
|
|
|
|||
|
|
@ -209,10 +209,13 @@ public:
|
|||
void IMAGE_ATOMIC(AtomicOp op, const GcnInst& inst);
|
||||
|
||||
private:
|
||||
template <typename T = IR::U32F32>
|
||||
[[nodiscard]] T GetSrc(const InstOperand& operand, bool integer = false);
|
||||
template <typename T = IR::U64F64>
|
||||
[[nodiscard]] T GetSrc64(const InstOperand& operand, bool flt_zero = false);
|
||||
struct SrcAuto;
|
||||
[[nodiscard]] IR::U32F32 GetSrcRaw(const InstOperand& operand, bool integer);
|
||||
[[nodiscard]] IR::U64F64 GetSrcRaw64(const InstOperand& operand, bool integer);
|
||||
|
||||
template <typename T = SrcAuto>
|
||||
[[nodiscard]] T GetSrc(const InstOperand& operand);
|
||||
|
||||
void SetDst(const InstOperand& operand, const IR::U32F32& value);
|
||||
void SetDst64(const InstOperand& operand, const IR::U64F64& value_raw);
|
||||
|
||||
|
|
@ -224,6 +227,25 @@ private:
|
|||
const Profile& profile;
|
||||
IR::U32 m0_value;
|
||||
bool opcode_missing = false;
|
||||
|
||||
class SrcAuto {
|
||||
Translator& translator;
|
||||
const InstOperand& operand;
|
||||
|
||||
public:
|
||||
SrcAuto(Translator& translator, const InstOperand& operand)
|
||||
: translator(translator), operand(operand) {}
|
||||
|
||||
operator IR::Value() const;
|
||||
|
||||
operator IR::U32F32() const;
|
||||
operator IR::U32() const;
|
||||
operator IR::F32() const;
|
||||
|
||||
operator IR::U64F64() const;
|
||||
operator IR::U64() const;
|
||||
operator IR::F64() const;
|
||||
};
|
||||
};
|
||||
|
||||
void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_list, Info& info,
|
||||
|
|
|
|||
|
|
@ -312,12 +312,18 @@ void Translator::V_MOV(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_SAD(const GcnInst& inst) {
|
||||
const IR::U32 abs_diff = ir.IAbs(ir.ISub(GetSrc(inst.src[0], true), GetSrc(inst.src[1], true)));
|
||||
SetDst(inst.dst[0], ir.IAdd(abs_diff, GetSrc(inst.src[2])));
|
||||
const IR::U32 src0 = GetSrc(inst.src[0]);
|
||||
const IR::U32 src1 = GetSrc(inst.src[1]);
|
||||
const IR::U32 src2 = GetSrc(inst.src[2]);
|
||||
const IR::U32 abs_diff = ir.IAbs(ir.ISub(src0, src1));
|
||||
SetDst(inst.dst[0], ir.IAdd(abs_diff, src2));
|
||||
}
|
||||
|
||||
void Translator::V_MAC_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], ir.FPFma(GetSrc(inst.src[0]), GetSrc(inst.src[1]), GetSrc(inst.dst[0])));
|
||||
const IR::F32 src0 = GetSrc(inst.src[0]);
|
||||
const IR::F32 src1 = GetSrc(inst.src[1]);
|
||||
const IR::F32 dst0 = GetSrc(inst.dst[0]);
|
||||
SetDst(inst.dst[0], ir.FPFma(src0, src1, dst0));
|
||||
}
|
||||
|
||||
void Translator::V_CVT_PKRTZ_F16_F32(const GcnInst& inst) {
|
||||
|
|
@ -339,7 +345,9 @@ void Translator::V_CVT_F16_F32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_MUL_F32(const GcnInst& inst) {
|
||||
SetDst(inst.dst[0], ir.FPMul(GetSrc(inst.src[0]), GetSrc(inst.src[1])));
|
||||
const IR::F32 src0 = GetSrc(inst.src[0]);
|
||||
const IR::F32 src1 = GetSrc(inst.src[1]);
|
||||
SetDst(inst.dst[0], ir.FPMul(src0, src1));
|
||||
}
|
||||
|
||||
void Translator::V_CNDMASK_B32(const GcnInst& inst) {
|
||||
|
|
@ -357,8 +365,8 @@ void Translator::V_CNDMASK_B32(const GcnInst& inst) {
|
|||
};
|
||||
const bool has_flt_source =
|
||||
is_float_const(inst.src[0].field) || is_float_const(inst.src[1].field);
|
||||
IR::U32F32 src0 = GetSrc(inst.src[0], has_flt_source);
|
||||
IR::U32F32 src1 = GetSrc(inst.src[1], has_flt_source);
|
||||
IR::U32F32 src0 = GetSrc(inst.src[0]);
|
||||
IR::U32F32 src1 = GetSrc(inst.src[1]);
|
||||
if (src0.Type() == IR::Type::F32 && src1.Type() == IR::Type::U32) {
|
||||
src1 = ir.BitCast<IR::F32, IR::U32>(src1);
|
||||
}
|
||||
|
|
@ -385,21 +393,21 @@ void Translator::V_AND_B32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_LSHLREV_B32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
ir.SetVectorReg(dst_reg, ir.ShiftLeftLogical(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F))));
|
||||
}
|
||||
|
||||
void Translator::V_LSHL_B32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F))));
|
||||
}
|
||||
|
||||
void Translator::V_ADD_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::VectorReg dst_reg{inst.dst[0].code};
|
||||
ir.SetVectorReg(dst_reg, ir.IAdd(src0, src1));
|
||||
// TODO: Carry
|
||||
|
|
@ -407,8 +415,8 @@ void Translator::V_ADD_I32(const GcnInst& inst) {
|
|||
|
||||
void Translator::V_ADDC_U32(const GcnInst& inst) {
|
||||
|
||||
const auto src0 = GetSrc<IR::U32>(inst.src[0], true);
|
||||
const auto src1 = GetSrc<IR::U32>(inst.src[1], true);
|
||||
const auto src0 = GetSrc<IR::U32>(inst.src[0]);
|
||||
const auto src1 = GetSrc<IR::U32>(inst.src[1]);
|
||||
|
||||
IR::U32 scarry;
|
||||
if (inst.src_count == 3) { // VOP3
|
||||
|
|
@ -549,8 +557,8 @@ void Translator::V_MAX_F32(const GcnInst& inst, bool is_legacy) {
|
|||
}
|
||||
|
||||
void Translator::V_MAX_U32(bool is_signed, const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.IMax(src0, src1, is_signed));
|
||||
}
|
||||
|
||||
|
|
@ -593,9 +601,9 @@ void Translator::V_MIN3_F32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_MIN3_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src2{GetSrc(inst.src[2], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U32 src2{GetSrc(inst.src[2])};
|
||||
SetDst(inst.dst[0], ir.SMin(src0, ir.SMin(src1, src2)));
|
||||
}
|
||||
|
||||
|
|
@ -634,16 +642,16 @@ void Translator::V_SUBREV_F32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_SUBREV_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ISub(src1, src0));
|
||||
// TODO: Carry-out
|
||||
}
|
||||
|
||||
void Translator::V_MAD_U64_U32(const GcnInst& inst) {
|
||||
const auto src0 = GetSrc<IR::U32>(inst.src[0], true);
|
||||
const auto src1 = GetSrc<IR::U32>(inst.src[1], true);
|
||||
const auto src2 = GetSrc64<IR::U64>(inst.src[2], true);
|
||||
const auto src0 = GetSrc<IR::U32>(inst.src[0]);
|
||||
const auto src1 = GetSrc<IR::U32>(inst.src[1]);
|
||||
const auto src2 = GetSrc<IR::U64>(inst.src[2]);
|
||||
|
||||
// const IR::U64 mul_result = ir.UConvert(64, ir.IMul(src0, src1));
|
||||
const IR::U64 mul_result =
|
||||
|
|
@ -659,8 +667,8 @@ void Translator::V_MAD_U64_U32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U1 result = [&] {
|
||||
switch (op) {
|
||||
case ConditionOp::F:
|
||||
|
|
@ -697,64 +705,64 @@ void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const
|
|||
}
|
||||
|
||||
void Translator::V_LSHRREV_B32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ShiftRightLogical(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F))));
|
||||
}
|
||||
|
||||
void Translator::V_MUL_HI_U32(bool is_signed, const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U32 hi{ir.CompositeExtract(ir.IMulExt(src0, src1, is_signed), 1)};
|
||||
SetDst(inst.dst[0], hi);
|
||||
}
|
||||
|
||||
void Translator::V_SAD_U32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src2{GetSrc(inst.src[2], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U32 src2{GetSrc(inst.src[2])};
|
||||
const IR::U32 max{ir.IMax(src0, src1, false)};
|
||||
const IR::U32 min{ir.IMin(src0, src1, false)};
|
||||
SetDst(inst.dst[0], ir.IAdd(ir.ISub(max, min), src2));
|
||||
}
|
||||
|
||||
void Translator::V_BFE_U32(bool is_signed, const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{ir.BitwiseAnd(GetSrc(inst.src[1], true), ir.Imm32(0x1F))};
|
||||
const IR::U32 src2{ir.BitwiseAnd(GetSrc(inst.src[2], true), ir.Imm32(0x1F))};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{ir.BitwiseAnd(GetSrc(inst.src[1]), ir.Imm32(0x1F))};
|
||||
const IR::U32 src2{ir.BitwiseAnd(GetSrc(inst.src[2]), ir.Imm32(0x1F))};
|
||||
SetDst(inst.dst[0], ir.BitFieldExtract(src0, src1, src2, is_signed));
|
||||
}
|
||||
|
||||
void Translator::V_MAD_I32_I24(const GcnInst& inst, bool is_signed) {
|
||||
const IR::U32 src0{
|
||||
ir.BitFieldExtract(GetSrc(inst.src[0], true), ir.Imm32(0), ir.Imm32(24), is_signed)};
|
||||
ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), is_signed)};
|
||||
const IR::U32 src1{
|
||||
ir.BitFieldExtract(GetSrc(inst.src[1], true), ir.Imm32(0), ir.Imm32(24), is_signed)};
|
||||
const IR::U32 src2{GetSrc(inst.src[2], true)};
|
||||
ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), is_signed)};
|
||||
const IR::U32 src2{GetSrc(inst.src[2])};
|
||||
SetDst(inst.dst[0], ir.IAdd(ir.IMul(src0, src1), src2));
|
||||
}
|
||||
|
||||
void Translator::V_MUL_I32_I24(const GcnInst& inst) {
|
||||
const IR::U32 src0{ir.BitFieldExtract(GetSrc(inst.src[0], true), ir.Imm32(0), ir.Imm32(24))};
|
||||
const IR::U32 src1{ir.BitFieldExtract(GetSrc(inst.src[1], true), ir.Imm32(0), ir.Imm32(24))};
|
||||
const IR::U32 src0{ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24))};
|
||||
const IR::U32 src1{ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24))};
|
||||
SetDst(inst.dst[0], ir.IMul(src0, src1));
|
||||
}
|
||||
|
||||
void Translator::V_SUB_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ISub(src0, src1));
|
||||
}
|
||||
|
||||
void Translator::V_LSHR_B32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ShiftRightLogical(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F))));
|
||||
}
|
||||
|
||||
void Translator::V_ASHRREV_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.ShiftRightArithmetic(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F))));
|
||||
}
|
||||
|
||||
|
|
@ -768,8 +776,8 @@ void Translator::V_RNDNE_F32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_BCNT_U32_B32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.IAdd(ir.BitCount(src0), src1));
|
||||
}
|
||||
|
||||
|
|
@ -786,9 +794,9 @@ void Translator::V_MAX3_F32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_MAX3_U32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src2{GetSrc(inst.src[2], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U32 src2{GetSrc(inst.src[2])};
|
||||
SetDst(inst.dst[0], ir.UMax(src0, ir.UMax(src1, src2)));
|
||||
}
|
||||
|
||||
|
|
@ -798,14 +806,14 @@ void Translator::V_CVT_I32_F32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_MIN_I32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.SMin(src0, src1));
|
||||
}
|
||||
|
||||
void Translator::V_MUL_LO_U32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.IMul(src0, src1));
|
||||
}
|
||||
|
||||
|
|
@ -820,8 +828,8 @@ void Translator::V_CEIL_F32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_MIN_U32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
SetDst(inst.dst[0], ir.IMin(src0, src1, false));
|
||||
}
|
||||
|
||||
|
|
@ -891,7 +899,7 @@ void Translator::V_CVT_FLR_I32_F32(const GcnInst& inst) {
|
|||
|
||||
void Translator::V_CMP_CLASS_F32(const GcnInst& inst) {
|
||||
const IR::F32F64 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
IR::U1 value;
|
||||
if (src1.IsImmediate()) {
|
||||
const auto class_mask = static_cast<IR::FloatClassFunc>(src1.U32());
|
||||
|
|
@ -916,13 +924,13 @@ void Translator::V_CMP_CLASS_F32(const GcnInst& inst) {
|
|||
}
|
||||
|
||||
void Translator::V_FFBL_B32(const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
SetDst(inst.dst[0], ir.FindILsb(src0));
|
||||
}
|
||||
|
||||
void Translator::V_MBCNT_U32_B32(bool is_low, const GcnInst& inst) {
|
||||
const IR::U32 src0{GetSrc(inst.src[0], true)};
|
||||
const IR::U32 src1{GetSrc(inst.src[1], true)};
|
||||
const IR::U32 src0{GetSrc(inst.src[0])};
|
||||
const IR::U32 src1{GetSrc(inst.src[1])};
|
||||
const IR::U32 lane_id = ir.LaneId();
|
||||
|
||||
const auto [warp_half, mask_shift] = [&]() -> std::pair<IR::U32, IR::U32> {
|
||||
|
|
|
|||
|
|
@ -933,18 +933,14 @@ F32F64 IREmitter::FPMin(const F32F64& lhs, const F32F64& rhs, bool is_legacy) {
|
|||
}
|
||||
}
|
||||
|
||||
U32U64 IREmitter::IAdd(const U32U64& a, const U32U64& b) {
|
||||
if (a.Type() != b.Type()) {
|
||||
UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
|
||||
}
|
||||
switch (a.Type()) {
|
||||
case Type::U32:
|
||||
return Inst<U32>(Opcode::IAdd32, a, b);
|
||||
case Type::U64:
|
||||
return Inst<U64>(Opcode::IAdd64, a, b);
|
||||
default:
|
||||
ThrowInvalidType(a.Type());
|
||||
}
|
||||
template <>
|
||||
U32 IREmitter::IAdd(const U32& a, const U32& b) {
|
||||
return Inst<U32>(Opcode::IAdd32, a, b);
|
||||
}
|
||||
|
||||
template <>
|
||||
U64 IREmitter::IAdd(const U64& a, const U64& b) {
|
||||
return Inst<U64>(Opcode::IAdd64, a, b);
|
||||
}
|
||||
|
||||
Value IREmitter::IAddCary(const U32& a, const U32& b) {
|
||||
|
|
@ -959,36 +955,28 @@ Value IREmitter::IAddCary(const U32& a, const U32& b) {
|
|||
}
|
||||
}
|
||||
|
||||
U32U64 IREmitter::ISub(const U32U64& a, const U32U64& b) {
|
||||
if (a.Type() != b.Type()) {
|
||||
UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
|
||||
}
|
||||
switch (a.Type()) {
|
||||
case Type::U32:
|
||||
return Inst<U32>(Opcode::ISub32, a, b);
|
||||
case Type::U64:
|
||||
return Inst<U64>(Opcode::ISub64, a, b);
|
||||
default:
|
||||
ThrowInvalidType(a.Type());
|
||||
}
|
||||
template <>
|
||||
U32 IREmitter::ISub(const U32& a, const U32& b) {
|
||||
return Inst<U32>(Opcode::ISub32, a, b);
|
||||
}
|
||||
|
||||
template <>
|
||||
U64 IREmitter::ISub(const U64& a, const U64& b) {
|
||||
return Inst<U64>(Opcode::ISub64, a, b);
|
||||
}
|
||||
|
||||
IR::Value IREmitter::IMulExt(const U32& a, const U32& b, bool is_signed) {
|
||||
return Inst(is_signed ? Opcode::SMulExt : Opcode::UMulExt, a, b);
|
||||
}
|
||||
|
||||
U32U64 IREmitter::IMul(const U32U64& a, const U32U64& b) {
|
||||
if (a.Type() != b.Type()) {
|
||||
UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
|
||||
}
|
||||
switch (a.Type()) {
|
||||
case Type::U32:
|
||||
return Inst<U32>(Opcode::IMul32, a, b);
|
||||
case Type::U64:
|
||||
return Inst<U64>(Opcode::IMul64, a, b);
|
||||
default:
|
||||
ThrowInvalidType(a.Type());
|
||||
}
|
||||
template <>
|
||||
U32 IREmitter::IMul(const U32& a, const U32& b) {
|
||||
return Inst<U32>(Opcode::IMul32, a, b);
|
||||
}
|
||||
|
||||
template <>
|
||||
U64 IREmitter::IMul(const U64& a, const U64& b) {
|
||||
return Inst<U64>(Opcode::IMul64, a, b);
|
||||
}
|
||||
|
||||
U32 IREmitter::IDiv(const U32& a, const U32& b, bool is_signed) {
|
||||
|
|
@ -1010,55 +998,45 @@ U32 IREmitter::IAbs(const U32& value) {
|
|||
return Inst<U32>(Opcode::IAbs32, value);
|
||||
}
|
||||
|
||||
U32U64 IREmitter::ShiftLeftLogical(const U32U64& base, const U32& shift) {
|
||||
switch (base.Type()) {
|
||||
case Type::U32:
|
||||
return Inst<U32>(Opcode::ShiftLeftLogical32, base, shift);
|
||||
case Type::U64:
|
||||
return Inst<U64>(Opcode::ShiftLeftLogical64, base, shift);
|
||||
default:
|
||||
ThrowInvalidType(base.Type());
|
||||
}
|
||||
template <>
|
||||
U32 IREmitter::ShiftLeftLogical(const U32& base, const U32& shift) {
|
||||
return Inst<U32>(Opcode::ShiftLeftLogical32, base, shift);
|
||||
}
|
||||
template <>
|
||||
U64 IREmitter::ShiftLeftLogical(const U64& base, const U32& shift) {
|
||||
return Inst<U64>(Opcode::ShiftLeftLogical64, base, shift);
|
||||
}
|
||||
|
||||
U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) {
|
||||
switch (base.Type()) {
|
||||
case Type::U32:
|
||||
return Inst<U32>(Opcode::ShiftRightLogical32, base, shift);
|
||||
case Type::U64:
|
||||
return Inst<U64>(Opcode::ShiftRightLogical64, base, shift);
|
||||
default:
|
||||
ThrowInvalidType(base.Type());
|
||||
}
|
||||
template <>
|
||||
U32 IREmitter::ShiftRightLogical(const U32& base, const U32& shift) {
|
||||
return Inst<U32>(Opcode::ShiftRightLogical32, base, shift);
|
||||
}
|
||||
template <>
|
||||
U64 IREmitter::ShiftRightLogical(const U64& base, const U32& shift) {
|
||||
return Inst<U64>(Opcode::ShiftRightLogical64, base, shift);
|
||||
}
|
||||
|
||||
U32U64 IREmitter::ShiftRightArithmetic(const U32U64& base, const U32& shift) {
|
||||
switch (base.Type()) {
|
||||
case Type::U32:
|
||||
return Inst<U32>(Opcode::ShiftRightArithmetic32, base, shift);
|
||||
case Type::U64:
|
||||
return Inst<U64>(Opcode::ShiftRightArithmetic64, base, shift);
|
||||
default:
|
||||
ThrowInvalidType(base.Type());
|
||||
}
|
||||
template <>
|
||||
U32 IREmitter::ShiftRightArithmetic(const U32& base, const U32& shift) {
|
||||
return Inst<U32>(Opcode::ShiftRightArithmetic32, base, shift);
|
||||
}
|
||||
template <>
|
||||
U64 IREmitter::ShiftRightArithmetic(const U64& base, const U32& shift) {
|
||||
return Inst<U64>(Opcode::ShiftRightArithmetic64, base, shift);
|
||||
}
|
||||
|
||||
U32 IREmitter::BitwiseAnd(const U32& a, const U32& b) {
|
||||
return Inst<U32>(Opcode::BitwiseAnd32, a, b);
|
||||
}
|
||||
|
||||
U32U64 IREmitter::BitwiseOr(const U32U64& a, const U32U64& b) {
|
||||
if (a.Type() != b.Type()) {
|
||||
UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
|
||||
}
|
||||
switch (a.Type()) {
|
||||
case Type::U32:
|
||||
return Inst<U32>(Opcode::BitwiseOr32, a, b);
|
||||
case Type::U64:
|
||||
return Inst<U64>(Opcode::BitwiseOr64, a, b);
|
||||
default:
|
||||
ThrowInvalidType(a.Type());
|
||||
}
|
||||
template <>
|
||||
U32 IREmitter::BitwiseOr(const U32& a, const U32& b) {
|
||||
return Inst<U32>(Opcode::BitwiseOr32, a, b);
|
||||
}
|
||||
|
||||
template <>
|
||||
U64 IREmitter::BitwiseOr(const U64& a, const U64& b) {
|
||||
return Inst<U64>(Opcode::BitwiseOr64, a, b);
|
||||
}
|
||||
|
||||
U32 IREmitter::BitwiseXor(const U32& a, const U32& b) {
|
||||
|
|
|
|||
|
|
@ -157,19 +157,26 @@ public:
|
|||
[[nodiscard]] F32F64 FPMax(const F32F64& lhs, const F32F64& rhs, bool is_legacy = false);
|
||||
[[nodiscard]] F32F64 FPMin(const F32F64& lhs, const F32F64& rhs, bool is_legacy = false);
|
||||
|
||||
[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
|
||||
template <typename T = U32>
|
||||
[[nodiscard]] T IAdd(const T& a, const T& b);
|
||||
[[nodiscard]] Value IAddCary(const U32& a, const U32& b);
|
||||
[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
|
||||
template <typename T = U32>
|
||||
[[nodiscard]] T ISub(const T& a, const T& b);
|
||||
[[nodiscard]] Value IMulExt(const U32& a, const U32& b, bool is_signed = false);
|
||||
[[nodiscard]] U32U64 IMul(const U32U64& a, const U32U64& b);
|
||||
template <typename T = U32>
|
||||
[[nodiscard]] T IMul(const T& a, const T& b);
|
||||
[[nodiscard]] U32 IDiv(const U32& a, const U32& b, bool is_signed = false);
|
||||
[[nodiscard]] U32U64 INeg(const U32U64& value);
|
||||
[[nodiscard]] U32 IAbs(const U32& value);
|
||||
[[nodiscard]] U32U64 ShiftLeftLogical(const U32U64& base, const U32& shift);
|
||||
[[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
|
||||
[[nodiscard]] U32U64 ShiftRightArithmetic(const U32U64& base, const U32& shift);
|
||||
template <typename T = U32>
|
||||
[[nodiscard]] T ShiftLeftLogical(const T& base, const U32& shift);
|
||||
template <typename T = U32>
|
||||
[[nodiscard]] T ShiftRightLogical(const T& base, const U32& shift);
|
||||
template <typename T = U32>
|
||||
[[nodiscard]] T ShiftRightArithmetic(const T& base, const U32& shift);
|
||||
[[nodiscard]] U32 BitwiseAnd(const U32& a, const U32& b);
|
||||
[[nodiscard]] U32U64 BitwiseOr(const U32U64& a, const U32U64& b);
|
||||
template <typename T = U32>
|
||||
[[nodiscard]] T BitwiseOr(const T& a, const T& b);
|
||||
[[nodiscard]] U32 BitwiseXor(const U32& a, const U32& b);
|
||||
[[nodiscard]] U32 BitFieldInsert(const U32& base, const U32& insert, const U32& offset,
|
||||
const U32& count);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue