hack: Fix swizzle on RDR

* Will properly fix this when merging this
This commit is contained in:
IndecisiveTurtle 2024-07-30 02:21:29 +03:00
parent 9ca91a1f15
commit 797b40f2e7
2 changed files with 18 additions and 1 deletions

View file

@ -351,7 +351,7 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
}
if (data_format == AmdGpu::DataFormat::Format8_8_8_8 &&
num_format == AmdGpu::NumberFormat::Unorm) {
return vk::Format::eR8G8B8A8Unorm;
return vk::Format::eB8G8R8A8Unorm;
}
if (data_format == AmdGpu::DataFormat::Format8_8_8_8 &&
num_format == AmdGpu::NumberFormat::Srgb) {

View file

@ -50,6 +50,15 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
UNREACHABLE();
}
scheduler.EndRendering();
const vk::MemoryBarrier barrier = {
.srcAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
.dstAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
};
cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eAllCommands,
vk::PipelineStageFlagBits::eAllCommands,
vk::DependencyFlagBits::eByRegion, barrier, {}, {});
BeginRendering();
UpdateDynamicState(*pipeline);
@ -92,6 +101,14 @@ void Rasterizer::DispatchDirect() {
}
scheduler.EndRendering();
const vk::MemoryBarrier barrier = {
.srcAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
.dstAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
};
cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eAllCommands,
vk::PipelineStageFlagBits::eAllCommands,
vk::DependencyFlagBits::eByRegion, barrier, {}, {});
cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, pipeline->Handle());
cmdbuf.dispatch(cs_program.dim_x, cs_program.dim_y, cs_program.dim_z);
}