Fix S_LSHR_B32 (#2405)
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the shift value should be extracted from the 5 least significant bits of the second operand (S1.u[4:0]), to ensure that the shift is limited to values ​​from 0 to 31, suitable for 32-bit operations

Instruction S_LSHR_B32
Description D.u = S0.u >> S1.u[4:0]. SCC = 1 if result is non-zero.
This commit is contained in:
DanielSvoboda 2025-02-12 11:31:19 -03:00 committed by GitHub
parent 2188895b40
commit 98eb8cb741
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@ -435,7 +435,8 @@ void Translator::S_LSHL_B64(const GcnInst& inst) {
void Translator::S_LSHR_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
const IR::U32 result{ir.ShiftRightLogical(src0, src1)};
const IR::U32 shift_amt = ir.BitwiseAnd(src1, ir.Imm32(0x1F));
const IR::U32 result = ir.ShiftRightLogical(src0, shift_amt);
SetDst(inst.dst[0], result);
ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
}