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https://github.com/shadps4-emu/shadPS4.git
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renderer_vulkan: added support for MSAA attachments
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parent
ff9850ca00
commit
a05d0063fc
9 changed files with 47 additions and 9 deletions
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@ -294,15 +294,19 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
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const IR::Inst* body = inst.Arg(1).InstRecursive();
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const IR::Inst* body = inst.Arg(1).InstRecursive();
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const auto [coords, arg] = [&] -> std::pair<IR::Value, IR::Value> {
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const auto [coords, arg] = [&] -> std::pair<IR::Value, IR::Value> {
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switch (image.GetType()) {
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switch (image.GetType()) {
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case AmdGpu::ImageType::Color1D:
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case AmdGpu::ImageType::Color1D: // x
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return {body->Arg(0), body->Arg(1)};
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return {body->Arg(0), body->Arg(1)};
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case AmdGpu::ImageType::Color1DArray:
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case AmdGpu::ImageType::Color1DArray: // x, slice
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case AmdGpu::ImageType::Color2D:
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[[fallthrough]];
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case AmdGpu::ImageType::Color2D: // x, y
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return {ir.CompositeConstruct(body->Arg(0), body->Arg(1)), body->Arg(2)};
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return {ir.CompositeConstruct(body->Arg(0), body->Arg(1)), body->Arg(2)};
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case AmdGpu::ImageType::Color2DArray:
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case AmdGpu::ImageType::Color2DArray: // x, y, slice
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case AmdGpu::ImageType::Color3D:
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[[fallthrough]];
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case AmdGpu::ImageType::Color2DMsaa: // x, y, frag
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[[fallthrough]];
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case AmdGpu::ImageType::Color3D: // x, y, z
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return {ir.CompositeConstruct(body->Arg(0), body->Arg(1), body->Arg(2)), body->Arg(3)};
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return {ir.CompositeConstruct(body->Arg(0), body->Arg(1), body->Arg(2)), body->Arg(3)};
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case AmdGpu::ImageType::Cube:
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case AmdGpu::ImageType::Cube: // x, y, face
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return {PatchCubeCoord(ir, body->Arg(0), body->Arg(1), body->Arg(2)), body->Arg(3)};
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return {PatchCubeCoord(ir, body->Arg(0), body->Arg(1), body->Arg(2)), body->Arg(3)};
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default:
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default:
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UNREACHABLE_MSG("Unknown image type {}", image.GetType());
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UNREACHABLE_MSG("Unknown image type {}", image.GetType());
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@ -791,6 +791,18 @@ struct Liverpool {
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BitField<1, 1, u32> stencil_clear_enable;
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BitField<1, 1, u32> stencil_clear_enable;
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};
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};
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union AaConfig {
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BitField<0, 3, u32> msaa_num_samples;
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BitField<4, 1, u32> aa_mask_centroid_dtmn;
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BitField<13, 4, u32> max_sample_dst;
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BitField<20, 3, u32> msaa_exposed_samples;
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BitField<24, 2, u32> detail_to_exposed_mode;
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u32 NumSamples() const {
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return 1 << msaa_num_samples;
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}
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};
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union Regs {
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union Regs {
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struct {
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struct {
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INSERT_PADDING_WORDS(0x2C08);
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INSERT_PADDING_WORDS(0x2C08);
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@ -858,7 +870,9 @@ struct Liverpool {
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u32 enable_primitive_id;
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u32 enable_primitive_id;
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INSERT_PADDING_WORDS(0xA2DF - 0xA2A1 - 1);
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INSERT_PADDING_WORDS(0xA2DF - 0xA2A1 - 1);
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PolygonOffset poly_offset;
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PolygonOffset poly_offset;
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INSERT_PADDING_WORDS(0xA318 - 0xA2DF - 5);
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INSERT_PADDING_WORDS(0xA2F8 - 0xA2DF - 5);
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AaConfig aa_config;
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INSERT_PADDING_WORDS(0xA318 - 0xA2F8 - 1);
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ColorBuffer color_buffers[NumColorBuffers];
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ColorBuffer color_buffers[NumColorBuffers];
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INSERT_PADDING_WORDS(0xC242 - 0xA390);
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INSERT_PADDING_WORDS(0xC242 - 0xA390);
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PrimitiveType primitive_type;
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PrimitiveType primitive_type;
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@ -1022,6 +1036,7 @@ static_assert(GFX6_3D_REG_INDEX(index_size) == 0xA29D);
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static_assert(GFX6_3D_REG_INDEX(index_buffer_type) == 0xA29F);
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static_assert(GFX6_3D_REG_INDEX(index_buffer_type) == 0xA29F);
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static_assert(GFX6_3D_REG_INDEX(enable_primitive_id) == 0xA2A1);
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static_assert(GFX6_3D_REG_INDEX(enable_primitive_id) == 0xA2A1);
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static_assert(GFX6_3D_REG_INDEX(poly_offset) == 0xA2DF);
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static_assert(GFX6_3D_REG_INDEX(poly_offset) == 0xA2DF);
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static_assert(GFX6_3D_REG_INDEX(aa_config) == 0xA2F8);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[0].base_address) == 0xA318);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[0].base_address) == 0xA318);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[0].pitch) == 0xA319);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[0].pitch) == 0xA319);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[0].slice) == 0xA31A);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[0].slice) == 0xA31A);
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@ -482,4 +482,17 @@ vk::ClearValue ColorBufferClearValue(const AmdGpu::Liverpool::ColorBuffer& color
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return {.color = color};
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return {.color = color};
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}
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}
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vk::SampleCountFlagBits NumSamples(u32 num_samples) {
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switch (num_samples) {
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case 1:
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return vk::SampleCountFlagBits::e1;
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case 2:
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return vk::SampleCountFlagBits::e2;
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case 4:
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return vk::SampleCountFlagBits::e4;
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default:
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UNREACHABLE();
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}
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}
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} // namespace Vulkan::LiverpoolToVK
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} // namespace Vulkan::LiverpoolToVK
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@ -48,6 +48,8 @@ vk::Format DepthFormat(Liverpool::DepthBuffer::ZFormat z_format,
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vk::ClearValue ColorBufferClearValue(const AmdGpu::Liverpool::ColorBuffer& color_buffer);
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vk::ClearValue ColorBufferClearValue(const AmdGpu::Liverpool::ColorBuffer& color_buffer);
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vk::SampleCountFlagBits NumSamples(u32 num_samples);
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void EmitQuadToTriangleListIndices(u8* out_indices, u32 num_vertices);
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void EmitQuadToTriangleListIndices(u8* out_indices, u32 num_vertices);
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} // namespace Vulkan::LiverpoolToVK
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} // namespace Vulkan::LiverpoolToVK
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@ -92,7 +92,7 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
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};
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};
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const vk::PipelineMultisampleStateCreateInfo multisampling = {
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const vk::PipelineMultisampleStateCreateInfo multisampling = {
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.rasterizationSamples = vk::SampleCountFlagBits::e1,
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.rasterizationSamples = LiverpoolToVK::NumSamples(key.num_samples),
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.sampleShadingEnable = false,
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.sampleShadingEnable = false,
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};
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};
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@ -38,6 +38,7 @@ struct GraphicsPipelineKey {
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float depth_bias_slope_factor;
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float depth_bias_slope_factor;
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float depth_bias_clamp;
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float depth_bias_clamp;
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u32 depth_bias_enable;
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u32 depth_bias_enable;
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u32 num_samples = 1;
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Liverpool::StencilControl stencil;
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Liverpool::StencilControl stencil;
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Liverpool::StencilRefMask stencil_ref_front;
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Liverpool::StencilRefMask stencil_ref_front;
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Liverpool::StencilRefMask stencil_ref_back;
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Liverpool::StencilRefMask stencil_ref_back;
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@ -205,6 +205,7 @@ bool Instance::CreateDevice() {
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.logicOp = features.logicOp,
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.logicOp = features.logicOp,
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.samplerAnisotropy = features.samplerAnisotropy,
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.samplerAnisotropy = features.samplerAnisotropy,
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.fragmentStoresAndAtomics = features.fragmentStoresAndAtomics,
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.fragmentStoresAndAtomics = features.fragmentStoresAndAtomics,
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.shaderStorageImageMultisample = true,
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.shaderClipDistance = features.shaderClipDistance,
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.shaderClipDistance = features.shaderClipDistance,
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},
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},
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},
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},
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@ -114,6 +114,7 @@ void PipelineCache::RefreshGraphicsKey() {
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key.cull_mode = regs.polygon_control.CullingMode();
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key.cull_mode = regs.polygon_control.CullingMode();
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key.clip_space = regs.clipper_control.clip_space;
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key.clip_space = regs.clipper_control.clip_space;
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key.front_face = regs.polygon_control.front_face;
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key.front_face = regs.polygon_control.front_face;
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key.num_samples = regs.aa_config.NumSamples();
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const auto& db = regs.depth_buffer;
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const auto& db = regs.depth_buffer;
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if (key.depth.depth_enable) {
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if (key.depth.depth_enable) {
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@ -252,6 +252,7 @@ Image::Image(const Vulkan::Instance& instance_, Vulkan::Scheduler& scheduler_,
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},
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},
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.mipLevels = static_cast<u32>(info.resources.levels),
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.mipLevels = static_cast<u32>(info.resources.levels),
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.arrayLayers = static_cast<u32>(info.resources.layers),
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.arrayLayers = static_cast<u32>(info.resources.layers),
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.samples = LiverpoolToVK::NumSamples(info.num_samples),
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.tiling = vk::ImageTiling::eOptimal,
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.tiling = vk::ImageTiling::eOptimal,
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.usage = usage,
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.usage = usage,
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.initialLayout = vk::ImageLayout::eUndefined,
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.initialLayout = vk::ImageLayout::eUndefined,
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@ -267,7 +268,7 @@ Image::Image(const Vulkan::Instance& instance_, Vulkan::Scheduler& scheduler_,
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}
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}
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Transit(vk::ImageLayout::eGeneral, vk::AccessFlagBits::eNone);
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Transit(vk::ImageLayout::eGeneral, vk::AccessFlagBits::eNone);
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}
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} // namespace VideoCore
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void Image::Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> dst_mask) {
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void Image::Transit(vk::ImageLayout dst_layout, vk::Flags<vk::AccessFlagBits> dst_mask) {
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if (dst_layout == layout && dst_mask == access_mask) {
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if (dst_layout == layout && dst_mask == access_mask) {
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