clang format

src/shader_recompiler/backend/spirv/spirv_emit_context.cpp

@@ -404,8 +404,8 @@ spv::ImageFormat GetFormat(const AmdGpu::Image& image) {
         image.GetNumberFmt() == AmdGpu::NumberFormat::Float) {
         return spv::ImageFormat::Rgba32f;
     }
-    UNREACHABLE_MSG("Unknown storage format data_format={}, num_format={}",
-                    image.GetDataFmt(), image.GetNumberFmt());
+    UNREACHABLE_MSG("Unknown storage format data_format={}, num_format={}", image.GetDataFmt(),
+                    image.GetNumberFmt());
 }
 
 Id ImageType(EmitContext& ctx, const ImageResource& desc, Id sampled_type) {

src/shader_recompiler/frontend/format.cpp

@@ -2779,11 +2779,9 @@ constexpr std::array<InstFormat, 256> InstructionFormatDS = {{
     // 60 = DS_READ_U16
     {InstClass::DsIdxRd, InstCategory::DataShare, 3, 1, ScalarType::Uint32, ScalarType::Uint32},
     // 61 = DS_CONSUME
-    {InstClass::DsAppendCon, InstCategory::DataShare, 3, 1, ScalarType::Uint32,
-     ScalarType::Uint32},
+    {InstClass::DsAppendCon, InstCategory::DataShare, 3, 1, ScalarType::Uint32, ScalarType::Uint32},
     // 62 = DS_APPEND
-    {InstClass::DsAppendCon, InstCategory::DataShare, 3, 1, ScalarType::Uint32,
-     ScalarType::Uint32},
+    {InstClass::DsAppendCon, InstCategory::DataShare, 3, 1, ScalarType::Uint32, ScalarType::Uint32},
     // 63 = DS_ORDERED_COUNT
     {InstClass::GdsOrdCnt, InstCategory::DataShare, 3, 1, ScalarType::Undefined,
      ScalarType::Undefined},

src/shader_recompiler/frontend/structured_control_flow.cpp

@@ -825,7 +825,8 @@ IR::AbstractSyntaxList BuildASL(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::
     GotoPass goto_pass{cfg, stmt_pool};
     Statement& root{goto_pass.RootStatement()};
     IR::AbstractSyntaxList syntax_list;
-    TranslatePass{inst_pool, block_pool, stmt_pool, root, syntax_list, cfg.inst_list, info, profile};
+    TranslatePass{inst_pool,   block_pool,    stmt_pool, root,
+                  syntax_list, cfg.inst_list, info,      profile};
     ASSERT_MSG(!info.translation_failed, "Shader translation has failed");
     return syntax_list;
 }

src/shader_recompiler/frontend/structured_control_flow.h

@@ -12,7 +12,7 @@
 namespace Shader {
 struct Info;
 struct Profile;
-}
+} // namespace Shader
 
 namespace Shader::Gcn {
 

src/shader_recompiler/frontend/translate/translate.cpp

@@ -494,8 +494,8 @@ void Translator::LogMissingOpcode(const GcnInst& inst) {
     info.translation_failed = true;
 }
 
-void Translate(IR::Block* block, u32 pc, std::span<const GcnInst> inst_list,
-               Info& info, const Profile& profile) {
+void Translate(IR::Block* block, u32 pc, std::span<const GcnInst> inst_list, Info& info,
+               const Profile& profile) {
     if (inst_list.empty()) {
         return;
     }

src/shader_recompiler/frontend/translate/translate.h

@@ -12,7 +12,7 @@
 namespace Shader {
 struct Info;
 struct Profile;
-}
+} // namespace Shader
 
 namespace Shader::Gcn {
 
@@ -226,7 +226,7 @@ private:
     bool opcode_missing = false;
 };
 
-void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_list,
-               Info& info, const Profile& profile);
+void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_list, Info& info,
+               const Profile& profile);
 
 } // namespace Shader::Gcn

src/shader_recompiler/frontend/translate/vector_alu.cpp

@@ -1,8 +1,8 @@
 // SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
-#include "shader_recompiler/profile.h"
 #include "shader_recompiler/frontend/translate/translate.h"
+#include "shader_recompiler/profile.h"
 
 namespace Shader::Gcn {
 
@@ -939,8 +939,7 @@ void Translator::V_MBCNT_U32_B32(bool is_low, const GcnInst& inst) {
 
     const IR::U32 thread_mask = ir.ISub(ir.ShiftLeftLogical(ir.Imm32(1), mask_shift), ir.Imm32(1));
     const IR::U1 is_odd_warp = ir.INotEqual(warp_half, ir.Imm32(0));
-    const IR::U32 mask = IR::U32{ir.Select(is_odd_warp,
-                                           is_low ? ir.Imm32(~0U) : thread_mask,
+    const IR::U32 mask = IR::U32{ir.Select(is_odd_warp, is_low ? ir.Imm32(~0U) : thread_mask,
                                            is_low ? thread_mask : ir.Imm32(0))};
     const IR::U32 masked_value = ir.BitwiseAnd(src0, mask);
     const IR::U32 result = ir.IAdd(src1, ir.BitCount(masked_value));

src/shader_recompiler/frontend/translate/vector_memory.cpp

@@ -244,7 +244,7 @@ void Translator::IMAGE_GATHER(const GcnInst& inst) {
     info.has_bias.Assign(flags.test(MimgModifier::LodBias));
     info.has_lod_clamp.Assign(flags.test(MimgModifier::LodClamp));
     info.force_level0.Assign(flags.test(MimgModifier::Level0));
-    //info.explicit_lod.Assign(explicit_lod);
+    // info.explicit_lod.Assign(explicit_lod);
     info.gather_comp.Assign(std::bit_width(mimg.dmask) - 1);
 
     // Issue IR instruction, leaving unknown fields blank to patch later.

src/shader_recompiler/ir/passes/resource_tracking_pass.cpp

@@ -485,7 +485,8 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
     const auto inst_info = inst.Flags<IR::TextureInstInfo>();
     if (image.GetType() == AmdGpu::ImageType::Invalid) {
         IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
-        inst.ReplaceUsesWith(ir.CompositeConstruct(ir.Imm32(0.f), ir.Imm32(0.f), ir.Imm32(0.f), ir.Imm32(0.f)));
+        inst.ReplaceUsesWith(
+            ir.CompositeConstruct(ir.Imm32(0.f), ir.Imm32(0.f), ir.Imm32(0.f), ir.Imm32(0.f)));
         return;
     }
     u32 image_binding = descriptors.Add(ImageResource{

src/shader_recompiler/recompiler.cpp

@@ -28,7 +28,8 @@ IR::BlockList GenerateBlocks(const IR::AbstractSyntaxList& syntax_list) {
 }
 
 IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Block>& block_pool,
-                             std::span<const u32> token, const Info&& info, const Profile& profile) {
+                             std::span<const u32> token, const Info&& info,
+                             const Profile& profile) {
     // Ensure first instruction is expected.
     constexpr u32 token_mov_vcchi = 0xBEEB03FF;
     ASSERT_MSG(token[0] == token_mov_vcchi, "First instruction is not s_mov_b32 vcc_hi, #imm");

src/video_core/renderer_vulkan/liverpool_to_vk.cpp

@@ -539,8 +539,7 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
         num_format == AmdGpu::NumberFormat::Snorm) {
         return vk::Format::eR8G8B8A8Snorm;
     }
-    if (data_format == AmdGpu::DataFormat::FormatBc6 &&
-        num_format == AmdGpu::NumberFormat::Unorm) {
+    if (data_format == AmdGpu::DataFormat::FormatBc6 && num_format == AmdGpu::NumberFormat::Unorm) {
         return vk::Format::eBc6HUfloatBlock;
     }
     UNREACHABLE_MSG("Unknown data_format={} and num_format={}", u32(data_format), u32(num_format));

src/video_core/renderer_vulkan/vk_instance.cpp

@@ -164,11 +164,9 @@ bool Instance::CreateDevice() {
         vk::PhysicalDeviceVulkan13Features,
         vk::PhysicalDeviceWorkgroupMemoryExplicitLayoutFeaturesKHR,
         vk::PhysicalDeviceDepthClipControlFeaturesEXT>();
-    const vk::StructureChain properties_chain =
-        physical_device.getProperties2<vk::PhysicalDeviceProperties2,
-                                       vk::PhysicalDevicePortabilitySubsetPropertiesKHR,
-                                       vk::PhysicalDeviceExternalMemoryHostPropertiesEXT,
-                                       vk::PhysicalDeviceVulkan11Properties>();
+    const vk::StructureChain properties_chain = physical_device.getProperties2<
+        vk::PhysicalDeviceProperties2, vk::PhysicalDevicePortabilitySubsetPropertiesKHR,
+        vk::PhysicalDeviceExternalMemoryHostPropertiesEXT, vk::PhysicalDeviceVulkan11Properties>();
     subgroup_size = properties_chain.get<vk::PhysicalDeviceVulkan11Properties>().subgroupSize;
     LOG_INFO(Render_Vulkan, "Physical device subgroup size {}", subgroup_size);
 

src/video_core/renderer_vulkan/vk_pipeline_cache.cpp

@@ -269,8 +269,8 @@ std::unique_ptr<GraphicsPipeline> PipelineCache::CreateGraphicsPipeline() {
             Shader::Info info = MakeShaderInfo(stage, pgm->user_data, regs);
             info.pgm_base = pgm->Address<uintptr_t>();
             info.pgm_hash = hash;
-            programs[i] = Shader::TranslateProgram(inst_pool, block_pool, code, std::move(info),
-                                                   profile);
+            programs[i] =
+                Shader::TranslateProgram(inst_pool, block_pool, code, std::move(info), profile);
 
             // Compile IR to SPIR-V
             auto spv_code = Shader::Backend::SPIRV::EmitSPIRV(profile, programs[i], binding);
@@ -310,8 +310,8 @@ std::unique_ptr<ComputePipeline> PipelineCache::CreateComputePipeline() {
         Shader::Info info =
             MakeShaderInfo(Shader::Stage::Compute, cs_pgm.user_data, liverpool->regs);
         info.pgm_base = cs_pgm.Address<uintptr_t>();
-        auto program = Shader::TranslateProgram(inst_pool, block_pool, code, std::move(info),
-                                                profile);
+        auto program =
+            Shader::TranslateProgram(inst_pool, block_pool, code, std::move(info), profile);
 
         // Compile IR to SPIR-V
         u32 binding{};

src/video_core/renderer_vulkan/vk_stream_buffer.cpp

@@ -226,7 +226,7 @@ void StreamBuffer::WaitPendingOperations(u64 requested_upper_bound) {
     while (requested_upper_bound > wait_bound && wait_cursor < *invalidation_mark) {
         auto& watch = previous_watches[wait_cursor];
         wait_bound = watch.upper_bound;
-        //scheduler.Wait(watch.tick);
+        // scheduler.Wait(watch.tick);
         ++wait_cursor;
     }
 }