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Handle IT_SET_QUEUE_REG and IT_SET_PREDICATION PM4 packets

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This commit is contained in:
Marcin Mikołajczyk 2024-10-02 18:46:30 +01:00
parent 7e533ccf50
commit a6f94105b1
2 changed files with 50 additions and 0 deletions
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13
src/video_core/amdgpu/liverpool.cpp
View file

@ -545,6 +545,11 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
}
break;
}
case PM4ItOpcode::SetPredication: {
const auto* set_predication = reinterpret_cast<const PM4CmdSetPredication*>(header);
LOG_WARNING(Lib_GnmDriver, "SetPredication ignored");
break;
}
default:
UNREACHABLE_MSG("Unknown PM4 type 3 opcode {:#x} with count {}",
static_cast<u32>(opcode), count);
@ -645,6 +650,14 @@ Liverpool::Task Liverpool::ProcessCompute(std::span<const u32> acb, int vqid) {
release_mem->SignalFence(Platform::InterruptId::Compute0RelMem); // <---
break;
}
case PM4ItOpcode::SetQueueReg: {
const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
// Find what is the value of QueueRegWordOffset?
// std::memcpy(&regs.reg_array[QueueRegWordOffset + set_data->reg_offset],
// header + 2, (count - 1) * sizeof(u32));
LOG_WARNING(Lib_GnmDriver, "SetQueueReg ignored, offset={:#x}, value={:#x}", u32(set_data->reg_offset), *(set_data->data));
break;
}
default:
UNREACHABLE_MSG("Unknown PM4 type 3 opcode {:#x} with count {}",
static_cast<u32>(opcode), count);

37
src/video_core/amdgpu/pm4_cmds.h
View file

@ -807,4 +807,41 @@ struct PM4CmdDrawIndexIndirect {
u32 draw_initiator; ///< Draw Initiator Register
};
struct PM4CmdSetPredication {
enum class Predication : u32 {
DrawIfNotVisibleOrOverflow = 0u,
DrawIfVisibleOrNoOverflow = 1u
};
enum class PredicationOp : u32 {
ClearPredicate = 0b000u,
SetZPassPredicate = 0b001u,
SetPrimCountPredicate = 0b010u,
};
enum class PredicationHint : u32 {
WaitUntilFinalZPassWritten = 0u,
DrawIfNotFinalZPassWritten = 1u
};
PM4Type3Header header; ///< header
union {
BitField<4, 28, u32> start_addr_lo; ///< Start address bits [31:4]
u32 dw1;
};
union {
BitField<0, 8, u32> start_addr_hi; ///< Start address bits [39:32] - taken from PAL
///< SI programming guide says it's 16 bits but that
///< overlaps with subsequent fields, so likely an error
BitField<8, 1, Predication> predication; ///< Predication boolean, valid for both ops
BitField<12, 1, PredicationHint> hint; ///< Only valid for ZPass/Occlusion Predicate
BitField<16, 3, PredicationOp> op; ///< Predicate operation
BitField<31, 1, u32> cont; ///< Continue set predication, true if subsequent packet
u32 dw2;
};
template <typename T>
T Address() const {
return reinterpret_cast<T>(start_addr_lo | u64(start_addr_hi) << 32);
}
};
} // namespace AmdGpu