mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2025-04-21 03:54:45 +00:00
log improvement ThrowInvalidType
This commit is contained in:
DanielSvoboda
GitHub
parent
7edd293201
commit
cf2a167943
1 changed files with 49 additions and 44 deletions
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@ -2,14 +2,19 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <bit>
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#include <source_location>
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/ir/ir_emitter.h"
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#include "shader_recompiler/ir/value.h"
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namespace Shader::IR {
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namespace {
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[[noreturn]] void ThrowInvalidType(Type type, const std::string& functionName) {
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UNREACHABLE_MSG("Invalid type= {}, functionName= {}", u32(type), functionName);
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[[noreturn]] void ThrowInvalidType(Type type,
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std::source_location loc = std::source_location::current()) {
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const std::string functionName = loc.function_name();
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const int lineNumber = loc.line();
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UNREACHABLE_MSG("Invalid type = {}, functionName = {}, line = {}", u32(type), functionName,
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lineNumber);
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}
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Value MakeLodClampPair(IREmitter& ir, const F32& bias_lod, const F32& lod_clamp) {
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@ -382,7 +387,7 @@ F32F64 IREmitter::FPAdd(const F32F64& a, const F32F64& b) {
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case Type::F64:
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return Inst<F64>(Opcode::FPAdd64, a, b);
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default:
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ThrowInvalidType(a.Type(), "FPAdd");
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ThrowInvalidType(a.Type());
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}
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}
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@ -394,7 +399,7 @@ F32F64 IREmitter::FPSub(const F32F64& a, const F32F64& b) {
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case Type::F32:
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return Inst<F32>(Opcode::FPSub32, a, b);
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default:
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ThrowInvalidType(a.Type(), "FPSub");
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ThrowInvalidType(a.Type());
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}
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}
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@ -412,7 +417,7 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2) {
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case Type::F64:
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return Inst(Opcode::CompositeConstructF64x2, e1, e2);
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default:
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ThrowInvalidType(e1.Type(), "CompositeConstruct 2 arg");
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ThrowInvalidType(e1.Type());
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}
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}
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@ -430,7 +435,7 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2, const Valu
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case Type::F64:
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return Inst(Opcode::CompositeConstructF64x3, e1, e2, e3);
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default:
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ThrowInvalidType(e1.Type(), "CompositeConstruct 3 arg");
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ThrowInvalidType(e1.Type());
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}
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}
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@ -450,7 +455,7 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2, const Valu
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case Type::F64:
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return Inst(Opcode::CompositeConstructF64x4, e1, e2, e3, e4);
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default:
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ThrowInvalidType(e1.Type(), "CompositeConstruct 4 arg");
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ThrowInvalidType(e1.Type());
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}
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}
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@ -487,7 +492,7 @@ Value IREmitter::CompositeExtract(const Value& vector, size_t element) {
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case Type::F64x4:
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return read(Opcode::CompositeExtractF64x4, 4);
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default:
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ThrowInvalidType(vector.Type(), "CompositeExtract");
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ThrowInvalidType(vector.Type());
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}
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}
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@ -524,7 +529,7 @@ Value IREmitter::CompositeInsert(const Value& vector, const Value& object, size_
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case Type::F64x4:
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return insert(Opcode::CompositeInsertF64x4, 4);
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default:
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ThrowInvalidType(vector.Type(), "CompositeInsert");
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ThrowInvalidType(vector.Type());
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}
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}
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@ -586,7 +591,7 @@ F32F64 IREmitter::FPMul(const F32F64& a, const F32F64& b) {
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case Type::F64:
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return Inst<F64>(Opcode::FPMul64, a, b);
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default:
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ThrowInvalidType(a.Type(), "FPMul");
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ThrowInvalidType(a.Type());
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}
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}
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@ -600,7 +605,7 @@ F32F64 IREmitter::FPFma(const F32F64& a, const F32F64& b, const F32F64& c) {
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case Type::F64:
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return Inst<F64>(Opcode::FPFma64, a, b, c);
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default:
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ThrowInvalidType(a.Type(), "FPFma");
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ThrowInvalidType(a.Type());
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}
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}
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@ -611,7 +616,7 @@ F32F64 IREmitter::FPAbs(const F32F64& value) {
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case Type::F64:
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return Inst<F64>(Opcode::FPAbs64, value);
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default:
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ThrowInvalidType(value.Type(), "FPAbs");
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ThrowInvalidType(value.Type());
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}
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}
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@ -622,7 +627,7 @@ F32F64 IREmitter::FPNeg(const F32F64& value) {
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case Type::F64:
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return Inst<F64>(Opcode::FPNeg64, value);
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default:
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ThrowInvalidType(value.Type(), "FPNeg");
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ThrowInvalidType(value.Type());
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}
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}
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@ -664,7 +669,7 @@ F32F64 IREmitter::FPRecip(const F32F64& value) {
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case Type::F64:
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return Inst<F64>(Opcode::FPRecip64, value);
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default:
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ThrowInvalidType(value.Type(), "FPRecip");
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ThrowInvalidType(value.Type());
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}
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}
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@ -675,7 +680,7 @@ F32F64 IREmitter::FPRecipSqrt(const F32F64& value) {
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case Type::F64:
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return Inst<F64>(Opcode::FPRecipSqrt64, value);
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default:
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ThrowInvalidType(value.Type(), "FPRecipSqrt");
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ThrowInvalidType(value.Type());
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}
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}
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@ -690,7 +695,7 @@ F32F64 IREmitter::FPSaturate(const F32F64& value) {
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case Type::F64:
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return Inst<F64>(Opcode::FPSaturate64, value);
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default:
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ThrowInvalidType(value.Type(), "FPSaturate");
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ThrowInvalidType(value.Type());
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}
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}
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@ -705,7 +710,7 @@ F32F64 IREmitter::FPClamp(const F32F64& value, const F32F64& min_value, const F3
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case Type::F64:
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return Inst<F64>(Opcode::FPClamp64, value, min_value, max_value);
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default:
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ThrowInvalidType(value.Type(), "FPClamp");
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ThrowInvalidType(value.Type());
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}
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}
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@ -716,7 +721,7 @@ F32F64 IREmitter::FPRoundEven(const F32F64& value) {
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case Type::F64:
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return Inst<F64>(Opcode::FPRoundEven64, value);
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default:
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ThrowInvalidType(value.Type(), "FPRoundEven");
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ThrowInvalidType(value.Type());
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}
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}
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@ -727,7 +732,7 @@ F32F64 IREmitter::FPFloor(const F32F64& value) {
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case Type::F64:
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return Inst<F64>(Opcode::FPFloor64, value);
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default:
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ThrowInvalidType(value.Type(), "FPFloor");
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ThrowInvalidType(value.Type());
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}
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}
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@ -738,7 +743,7 @@ F32F64 IREmitter::FPCeil(const F32F64& value) {
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case Type::F64:
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return Inst<F64>(Opcode::FPCeil64, value);
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default:
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ThrowInvalidType(value.Type(), "FPCeil");
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ThrowInvalidType(value.Type());
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}
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}
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@ -749,7 +754,7 @@ F32F64 IREmitter::FPTrunc(const F32F64& value) {
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case Type::F64:
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return Inst<F64>(Opcode::FPTrunc64, value);
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default:
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ThrowInvalidType(value.Type(), "FPTrunc");
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ThrowInvalidType(value.Type());
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}
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}
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@ -767,7 +772,7 @@ U1 IREmitter::FPEqual(const F32F64& lhs, const F32F64& rhs, bool ordered) {
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case Type::F64:
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return Inst<U1>(ordered ? Opcode::FPOrdEqual64 : Opcode::FPUnordEqual64, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type(), "FPEqual");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -781,7 +786,7 @@ U1 IREmitter::FPNotEqual(const F32F64& lhs, const F32F64& rhs, bool ordered) {
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case Type::F64:
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return Inst<U1>(ordered ? Opcode::FPOrdNotEqual64 : Opcode::FPUnordNotEqual64, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type(), "FPNotEqual");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -795,7 +800,7 @@ U1 IREmitter::FPLessThan(const F32F64& lhs, const F32F64& rhs, bool ordered) {
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case Type::F64:
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return Inst<U1>(ordered ? Opcode::FPOrdLessThan64 : Opcode::FPUnordLessThan64, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type(), "FPLessThan");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -811,7 +816,7 @@ U1 IREmitter::FPGreaterThan(const F32F64& lhs, const F32F64& rhs, bool ordered)
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return Inst<U1>(ordered ? Opcode::FPOrdGreaterThan64 : Opcode::FPUnordGreaterThan64, lhs,
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rhs);
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default:
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ThrowInvalidType(lhs.Type(), "FPGreaterThan");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -827,7 +832,7 @@ U1 IREmitter::FPLessThanEqual(const F32F64& lhs, const F32F64& rhs, bool ordered
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return Inst<U1>(ordered ? Opcode::FPOrdLessThanEqual64 : Opcode::FPUnordLessThanEqual64,
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lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type(), "FPLessThanEqual");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -845,7 +850,7 @@ U1 IREmitter::FPGreaterThanEqual(const F32F64& lhs, const F32F64& rhs, bool orde
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: Opcode::FPUnordGreaterThanEqual64,
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lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type(), "FPGreaterThanEqual");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -856,7 +861,7 @@ U1 IREmitter::FPIsNan(const F32F64& value) {
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case Type::F64:
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return Inst<U1>(Opcode::FPIsNan64, value);
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default:
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ThrowInvalidType(value.Type(), "FPIsNan");
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ThrowInvalidType(value.Type());
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}
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}
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@ -867,7 +872,7 @@ U1 IREmitter::FPIsInf(const F32F64& value) {
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case Type::F64:
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return Inst<U1>(Opcode::FPIsInf64, value);
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default:
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ThrowInvalidType(value.Type(), "FPIsInf");
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ThrowInvalidType(value.Type());
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}
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}
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@ -899,7 +904,7 @@ F32F64 IREmitter::FPMax(const F32F64& lhs, const F32F64& rhs, bool is_legacy) {
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}
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return Inst<F64>(Opcode::FPMax64, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type(), "FPMax");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -916,7 +921,7 @@ F32F64 IREmitter::FPMin(const F32F64& lhs, const F32F64& rhs, bool is_legacy) {
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}
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return Inst<F64>(Opcode::FPMin64, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type(), "FPMin");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -930,7 +935,7 @@ U32U64 IREmitter::IAdd(const U32U64& a, const U32U64& b) {
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case Type::U64:
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return Inst<U64>(Opcode::IAdd64, a, b);
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default:
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ThrowInvalidType(a.Type(), "IAdd");
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ThrowInvalidType(a.Type());
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}
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}
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@ -942,7 +947,7 @@ Value IREmitter::IAddCary(const U32& a, const U32& b) {
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case Type::U32:
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return Inst<U32>(Opcode::IAddCary32, a, b);
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default:
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ThrowInvalidType(a.Type(), "IAddCary");
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ThrowInvalidType(a.Type());
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}
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}
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@ -956,7 +961,7 @@ U32U64 IREmitter::ISub(const U32U64& a, const U32U64& b) {
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case Type::U64:
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return Inst<U64>(Opcode::ISub64, a, b);
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default:
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ThrowInvalidType(a.Type(), "ISub");
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ThrowInvalidType(a.Type());
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}
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}
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@ -974,7 +979,7 @@ U32U64 IREmitter::IMul(const U32U64& a, const U32U64& b) {
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case Type::U64:
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return Inst<U64>(Opcode::IMul64, a, b);
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default:
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ThrowInvalidType(a.Type(), "IMul");
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ThrowInvalidType(a.Type());
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}
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}
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@ -989,7 +994,7 @@ U32U64 IREmitter::INeg(const U32U64& value) {
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case Type::U64:
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return Inst<U64>(Opcode::INeg64, value);
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default:
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ThrowInvalidType(value.Type(), "INeg");
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ThrowInvalidType(value.Type());
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}
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}
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@ -1004,7 +1009,7 @@ U32U64 IREmitter::ShiftLeftLogical(const U32U64& base, const U32& shift) {
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case Type::U64:
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return Inst<U64>(Opcode::ShiftLeftLogical64, base, shift);
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default:
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ThrowInvalidType(base.Type(), "ShiftLeftLogical");
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ThrowInvalidType(base.Type());
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}
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}
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@ -1015,7 +1020,7 @@ U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) {
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case Type::U64:
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return Inst<U64>(Opcode::ShiftRightLogical64, base, shift);
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default:
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ThrowInvalidType(base.Type(), "ShiftRightLogical");
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ThrowInvalidType(base.Type());
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}
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}
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@ -1026,7 +1031,7 @@ U32U64 IREmitter::ShiftRightArithmetic(const U32U64& base, const U32& shift) {
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case Type::U64:
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return Inst<U64>(Opcode::ShiftRightArithmetic64, base, shift);
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default:
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ThrowInvalidType(base.Type(), "ShiftRightArithmetic");
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ThrowInvalidType(base.Type());
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}
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}
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@ -1044,7 +1049,7 @@ U32U64 IREmitter::BitwiseOr(const U32U64& a, const U32U64& b) {
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case Type::U64:
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return Inst<U64>(Opcode::BitwiseOr64, a, b);
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default:
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ThrowInvalidType(a.Type(), "BitwiseOr");
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ThrowInvalidType(a.Type());
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}
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}
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@ -1125,7 +1130,7 @@ U1 IREmitter::ILessThan(const U32U64& lhs, const U32U64& rhs, bool is_signed) {
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case Type::U64:
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return Inst<U1>(is_signed ? Opcode::SLessThan64 : Opcode::ULessThan64, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type(), "ILessThan");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -1137,7 +1142,7 @@ U1 IREmitter::IEqual(const U32U64& lhs, const U32U64& rhs) {
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case Type::U32:
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return Inst<U1>(Opcode::IEqual, lhs, rhs);
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default:
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ThrowInvalidType(lhs.Type(), "IEqual");
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ThrowInvalidType(lhs.Type());
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}
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}
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@ -1182,7 +1187,7 @@ U32U64 IREmitter::ConvertFToS(size_t bitsize, const F32F64& value) {
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case Type::F64:
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return Inst<U32>(Opcode::ConvertS32F64, value);
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default:
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ThrowInvalidType(value.Type(), "ConvertFToS");
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ThrowInvalidType(value.Type());
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}
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default:
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break;
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@ -1197,7 +1202,7 @@ U32U64 IREmitter::ConvertFToU(size_t bitsize, const F32F64& value) {
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case Type::F32:
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return Inst<U32>(Opcode::ConvertU32F32, value);
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default:
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ThrowInvalidType(value.Type(), "ConvertFToU");
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ThrowInvalidType(value.Type());
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}
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default:
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UNREACHABLE_MSG("Invalid destination bitsize {}", bitsize);
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