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follow 32 convention

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microsoftv 2024-08-25 21:12:20 -04:00
parent 4b054b3eab
commit d142708af5
6 changed files with 7 additions and 7 deletions
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2
src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp
View file

@ -102,7 +102,7 @@ Id EmitBufferAtomicXor32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addres
return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicXor);
}
Id EmitBufferAtomicSwap(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
Id EmitBufferAtomicSwap32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicExchange);
}

2
src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
View file

@ -91,7 +91,7 @@ Id EmitBufferAtomicDec32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addres
Id EmitBufferAtomicAnd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicOr32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicXor32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicSwap(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicSwap32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp);
Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, u32 comp);
void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 comp);

2
src/shader_recompiler/ir/ir_emitter.cpp
View file

@ -406,7 +406,7 @@ Value IREmitter::BufferAtomicXor(const Value& handle, const Value& address, cons
Value IREmitter::BufferAtomicSwap(const Value& handle, const Value& address, const Value& value,
BufferInstInfo info) {
return Inst(Opcode::BufferAtomicSwap, Flags{info}, handle, address, value);
return Inst(Opcode::BufferAtomicSwap32, Flags{info}, handle, address, value);
}
void IREmitter::StoreBufferFormat(int num_dwords, const Value& handle, const Value& address,

2
src/shader_recompiler/ir/microinstruction.cpp
View file

@ -70,7 +70,7 @@ bool Inst::MayHaveSideEffects() const noexcept {
case Opcode::BufferAtomicAnd32:
case Opcode::BufferAtomicOr32:
case Opcode::BufferAtomicXor32:
case Opcode::BufferAtomicSwap:
case Opcode::BufferAtomicSwap32:
case Opcode::WriteSharedU128:
case Opcode::WriteSharedU64:
case Opcode::WriteSharedU32:

2
src/shader_recompiler/ir/opcodes.inc
View file

@ -105,7 +105,7 @@ OPCODE(BufferAtomicDec32, U32, Opaq
OPCODE(BufferAtomicAnd32, U32, Opaque, Opaque, U32, )
OPCODE(BufferAtomicOr32, U32, Opaque, Opaque, U32, )
OPCODE(BufferAtomicXor32, U32, Opaque, Opaque, U32, )
OPCODE(BufferAtomicSwap, U32, Opaque, Opaque, U32, )
OPCODE(BufferAtomicSwap32, U32, Opaque, Opaque, U32, )
// Vector utility
OPCODE(CompositeConstructU32x2, U32x2, U32, U32, )

4
src/shader_recompiler/ir/passes/resource_tracking_pass.cpp
View file

@ -32,7 +32,7 @@ bool IsBufferAtomic(const IR::Inst& inst) {
case IR::Opcode::BufferAtomicAnd32:
case IR::Opcode::BufferAtomicOr32:
case IR::Opcode::BufferAtomicXor32:
case IR::Opcode::BufferAtomicSwap:
case IR::Opcode::BufferAtomicSwap32:
return true;
default:
return false;
@ -136,7 +136,7 @@ IR::Type BufferDataType(const IR::Inst& inst, AmdGpu::NumberFormat num_format) {
case IR::Opcode::ReadConstBufferU32:
case IR::Opcode::StoreBufferU32:
case IR::Opcode::BufferAtomicIAdd32:
case IR::Opcode::BufferAtomicSwap:
case IR::Opcode::BufferAtomicSwap32:
return IR::Type::U32;
default:
UNREACHABLE();