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shader_recompiler: Define fragment output type based on number format.

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This commit is contained in:
squidbus 2024-09-26 18:32:08 -07:00
parent ebebafed64
commit d43ded07ac
7 changed files with 75 additions and 29 deletions
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44
src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
View file

@ -49,12 +49,13 @@ Id OutputAttrPointer(EmitContext& ctx, IR::Attribute attr, u32 element) {
if (info.num_components == 1) {
return info.id;
} else {
return ctx.OpAccessChain(ctx.output_f32, info.id, ctx.ConstU32(element));
return ctx.OpAccessChain(info.pointer_type, info.id, ctx.ConstU32(element));
}
}
switch (attr) {
case IR::Attribute::Position0: {
return ctx.OpAccessChain(ctx.output_f32, ctx.output_position, ctx.ConstU32(element));
}
case IR::Attribute::Position1:
case IR::Attribute::Position2:
case IR::Attribute::Position3: {
@ -70,17 +71,47 @@ Id OutputAttrPointer(EmitContext& ctx, IR::Attribute attr, u32 element) {
case IR::Attribute::RenderTarget6:
case IR::Attribute::RenderTarget7: {
const u32 index = u32(attr) - u32(IR::Attribute::RenderTarget0);
if (ctx.frag_num_comp[index] > 1) {
return ctx.OpAccessChain(ctx.output_f32, ctx.frag_color[index], ctx.ConstU32(element));
const auto& info{ctx.frag_outputs.at(index)};
if (info.num_components > 1) {
return ctx.OpAccessChain(info.pointer_type, info.id, ctx.ConstU32(element));
} else {
return ctx.frag_color[index];
return info.id;
}
}
case IR::Attribute::Depth:
return ctx.frag_depth;
default:
throw NotImplementedException("Read attribute {}", attr);
throw NotImplementedException("Write attribute {}", attr);
}
}
Id OutputAttrComponentType(EmitContext& ctx, IR::Attribute attr) {
if (IR::IsParam(attr)) {
const u32 index{u32(attr) - u32(IR::Attribute::Param0)};
const auto& info{ctx.output_params.at(index)};
return info.component_type;
}
switch (attr) {
case IR::Attribute::Position0:
case IR::Attribute::Position1:
case IR::Attribute::Position2:
case IR::Attribute::Position3:
case IR::Attribute::Depth:
return ctx.F32[1];
case IR::Attribute::RenderTarget0:
case IR::Attribute::RenderTarget1:
case IR::Attribute::RenderTarget2:
case IR::Attribute::RenderTarget3:
case IR::Attribute::RenderTarget4:
case IR::Attribute::RenderTarget5:
case IR::Attribute::RenderTarget6:
case IR::Attribute::RenderTarget7: {
const u32 index = u32(attr) - u32(IR::Attribute::RenderTarget0);
const auto& info{ctx.frag_outputs.at(index)};
return info.component_type;
}
default:
throw NotImplementedException("Write attribute {}", attr);
}
}
} // Anonymous namespace
@ -222,7 +253,8 @@ void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 elemen
return;
}
const Id pointer{OutputAttrPointer(ctx, attr, element)};
ctx.OpStore(pointer, ctx.OpBitcast(ctx.F32[1], value));
const Id component_type{OutputAttrComponentType(ctx, attr)};
ctx.OpStore(pointer, ctx.OpBitcast(component_type, value));
}
template <u32 N>

29
src/shader_recompiler/backend/spirv/spirv_emit_context.cpp
View file

@ -120,6 +120,7 @@ void EmitContext::DefineArithmeticTypes() {
output_f32 = Name(TypePointer(spv::StorageClass::Output, F32[1]), "output_f32");
output_u32 = Name(TypePointer(spv::StorageClass::Output, U32[1]), "output_u32");
output_s32 = Name(TypePointer(spv::StorageClass::Output, S32[1]), "output_s32");
full_result_i32x2 = Name(TypeStruct(S32[1], S32[1]), "full_result_i32x2");
full_result_u32x2 = Name(TypeStruct(U32[1], U32[1]), "full_result_u32x2");
@ -151,21 +152,21 @@ const VectorIds& GetAttributeType(EmitContext& ctx, AmdGpu::NumberFormat fmt) {
UNREACHABLE_MSG("Invalid attribute type {}", fmt);
}
EmitContext::SpirvAttribute EmitContext::GetAttributeInfo(AmdGpu::NumberFormat fmt, Id id) {
EmitContext::SpirvAttribute EmitContext::GetAttributeInfo(AmdGpu::NumberFormat fmt, Id id,
bool output) {
switch (fmt) {
case AmdGpu::NumberFormat::Float:
case AmdGpu::NumberFormat::Unorm:
case AmdGpu::NumberFormat::Snorm:
case AmdGpu::NumberFormat::SnormNz:
return {id, input_f32, F32[1], 4};
case AmdGpu::NumberFormat::Uint:
return {id, input_u32, U32[1], 4};
case AmdGpu::NumberFormat::Sint:
return {id, input_s32, S32[1], 4};
case AmdGpu::NumberFormat::Sscaled:
return {id, input_f32, F32[1], 4};
case AmdGpu::NumberFormat::Uscaled:
return {id, input_f32, F32[1], 4};
case AmdGpu::NumberFormat::Srgb:
return {id, output ? output_f32 : input_f32, F32[1], 4};
case AmdGpu::NumberFormat::Uint:
return {id, output ? output_u32 : input_u32, U32[1], 4};
case AmdGpu::NumberFormat::Sint:
return {id, output ? output_s32 : input_s32, S32[1], 4};
default:
break;
}
@ -247,7 +248,7 @@ void EmitContext::DefineInputs() {
} else {
Name(id, fmt::format("vs_in_attr{}", input.binding));
}
input_params[input.binding] = GetAttributeInfo(input.fmt, id);
input_params[input.binding] = GetAttributeInfo(input.fmt, id, false);
interfaces.push_back(id);
}
}
@ -320,10 +321,12 @@ void EmitContext::DefineOutputs() {
continue;
}
const u32 num_components = info.stores.NumComponents(mrt);
frag_color[i] = DefineOutput(F32[num_components], i);
frag_num_comp[i] = num_components;
Name(frag_color[i], fmt::format("frag_color{}", i));
interfaces.push_back(frag_color[i]);
const AmdGpu::NumberFormat num_format{runtime_info.fs_info.color_buffers[i].num_format};
const Id type{GetAttributeType(*this, num_format)[num_components]};
const Id id = DefineOutput(type, i);
Name(id, fmt::format("frag_color{}", i));
frag_outputs[i] = GetAttributeInfo(num_format, id, true);
interfaces.push_back(id);
}
break;
default:

6
src/shader_recompiler/backend/spirv/spirv_emit_context.h
View file

@ -166,6 +166,7 @@ public:
Id input_s32{};
Id output_u32{};
Id output_f32{};
Id output_s32{};
boost::container::small_vector<Id, 16> interfaces;
@ -177,8 +178,6 @@ public:
Id frag_coord{};
Id front_facing{};
Id frag_depth{};
std::array<Id, 8> frag_color{};
std::array<u32, 8> frag_num_comp{};
Id clip_distances{};
Id cull_distances{};
@ -242,6 +241,7 @@ public:
};
std::array<SpirvAttribute, 32> input_params{};
std::array<SpirvAttribute, 32> output_params{};
std::array<SpirvAttribute, 8> frag_outputs{};
private:
void DefineArithmeticTypes();
@ -254,7 +254,7 @@ private:
void DefineImagesAndSamplers();
void DefineSharedMemory();
SpirvAttribute GetAttributeInfo(AmdGpu::NumberFormat fmt, Id id);
SpirvAttribute GetAttributeInfo(AmdGpu::NumberFormat fmt, Id id, bool output);
};
} // namespace Shader::Backend::SPIRV

2
src/shader_recompiler/frontend/translate/export.cpp
View file

@ -25,7 +25,7 @@ void Translator::EmitExport(const GcnInst& inst) {
return comp;
}
const u32 index = u32(attrib) - u32(IR::Attribute::RenderTarget0);
switch (runtime_info.fs_info.mrt_swizzles[index]) {
switch (runtime_info.fs_info.color_buffers[index].mrt_swizzle) {
case MrtSwizzle::Identity:
return comp;
case MrtSwizzle::Alt:

10
src/shader_recompiler/runtime_info.h
View file

@ -80,10 +80,16 @@ struct FragmentRuntimeInfo {
auto operator<=>(const PsInput&) const noexcept = default;
};
boost::container::static_vector<PsInput, 32> inputs;
std::array<MrtSwizzle, MaxColorBuffers> mrt_swizzles;
struct PsColorBuffer {
AmdGpu::NumberFormat num_format;
MrtSwizzle mrt_swizzle;
auto operator<=>(const PsColorBuffer&) const noexcept = default;
};
std::array<PsColorBuffer, MaxColorBuffers> color_buffers;
bool operator==(const FragmentRuntimeInfo& other) const noexcept {
return std::ranges::equal(mrt_swizzles, other.mrt_swizzles) &&
return std::ranges::equal(color_buffers, other.color_buffers) &&
std::ranges::equal(inputs, other.inputs);
}
};

1
src/video_core/renderer_vulkan/vk_graphics_pipeline.h
View file

@ -26,6 +26,7 @@ using Liverpool = AmdGpu::Liverpool;
struct GraphicsPipelineKey {
std::array<size_t, MaxShaderStages> stage_hashes;
std::array<vk::Format, Liverpool::NumColorBuffers> color_formats;
std::array<AmdGpu::NumberFormat, Liverpool::NumColorBuffers> color_num_formats;
std::array<Liverpool::ColorBuffer::SwapMode, Liverpool::NumColorBuffers> mrt_swizzles;
vk::Format depth_format;
vk::Format stencil_format;

12
src/video_core/renderer_vulkan/vk_pipeline_cache.cpp
View file

@ -95,10 +95,6 @@ Shader::RuntimeInfo PipelineCache::BuildRuntimeInfo(Shader::Stage stage) {
case Shader::Stage::Fragment: {
info.num_user_data = regs.ps_program.settings.num_user_regs;
info.num_allocated_vgprs = regs.ps_program.settings.num_vgprs * 4;
std::ranges::transform(graphics_key.mrt_swizzles, info.fs_info.mrt_swizzles.begin(),
[](Liverpool::ColorBuffer::SwapMode mode) {
return static_cast<Shader::MrtSwizzle>(mode);
});
const auto& ps_inputs = regs.ps_inputs;
for (u32 i = 0; i < regs.num_interp; i++) {
info.fs_info.inputs.push_back({
@ -108,6 +104,12 @@ Shader::RuntimeInfo PipelineCache::BuildRuntimeInfo(Shader::Stage stage) {
.default_value = u8(ps_inputs[i].default_value),
});
}
for (u32 i = 0; i < Shader::MaxColorBuffers; i++) {
info.fs_info.color_buffers[i] = {
.num_format = graphics_key.color_num_formats[i],
.mrt_swizzle = static_cast<Shader::MrtSwizzle>(graphics_key.mrt_swizzles[i]),
};
}
break;
}
case Shader::Stage::Compute: {
@ -244,6 +246,7 @@ bool PipelineCache::RefreshGraphicsKey() {
// attachments. This might be not a case as HW color buffers can be bound in an arbitrary
// order. We need to do some arrays compaction at this stage
key.color_formats.fill(vk::Format::eUndefined);
key.color_num_formats.fill(AmdGpu::NumberFormat::Unorm);
key.blend_controls.fill({});
key.write_masks.fill({});
key.mrt_swizzles.fill(Liverpool::ColorBuffer::SwapMode::Standard);
@ -260,6 +263,7 @@ bool PipelineCache::RefreshGraphicsKey() {
const bool is_vo_surface = renderer->IsVideoOutSurface(col_buf);
key.color_formats[remapped_cb] = LiverpoolToVK::AdjustColorBufferFormat(
base_format, col_buf.info.comp_swap.Value(), false /*is_vo_surface*/);
key.color_num_formats[remapped_cb] = col_buf.NumFormat();
if (base_format == key.color_formats[remapped_cb]) {
key.mrt_swizzles[remapped_cb] = col_buf.info.comp_swap.Value();
}