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Clang Format & UNREACHABLE_MSG

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microsoftv 2024-08-14 02:26:05 -04:00
parent 600e1bc888
commit d4dab94acd
3 changed files with 12 additions and 16 deletions
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17
src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp
View file

@ -12,14 +12,11 @@ std::pair<Id, Id> AtomicArgs(EmitContext& ctx) {
return {scope, semantics};
}
Id BufferAtomicU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value,
Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
auto& buffer = ctx.buffers[handle];
address =
ctx.OpIAdd(ctx.U32[1], address, buffer.offset);
const Id index =
ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
address = ctx.OpIAdd(ctx.U32[1], address, buffer.offset);
const Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
const Id pointer{ctx.OpAccessChain(buffer.pointer_type, buffer.id, ctx.u32_zero_value, index)};
const auto [scope, semantics]{AtomicArgs(ctx)};
return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics, value);
@ -55,13 +52,13 @@ Id EmitBufferAtomicUMax32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addre
}
Id EmitBufferAtomicInc32(EmitContext&, IR::Inst*, u32, Id, Id) {
// TODO: This is not yet implemented
throw NotImplementedException("SPIR-V Instruction");
// TODO
UNREACHABLE_MSG("Unsupported BUFFER_ATOMIC opcode: ", IR::Opcode::BufferAtomicInc32);
}
Id EmitBufferAtomicDec32(EmitContext&, IR::Inst*, u32, Id, Id) {
// TODO: This is not yet implemented
throw NotImplementedException("SPIR-V Instruction");
Id EmitBufferAtomicDec32(EmitContext&, IR::Inst*, u32, Id, Id){
// TODO
UNREACHABLE_MSG("Unsupported BUFFER_ATOMIC opcode: ", IR::Opcode::BufferAtomicDec32);
}
Id EmitBufferAtomicAnd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {

6
src/shader_recompiler/frontend/translate/vector_memory.cpp
View file

@ -424,10 +424,10 @@ void Translator::BUFFER_ATOMIC(AtomicOp op, const GcnInst& inst) {
const IR::Value address = [&]() -> IR::Value {
if (mtbuf.idxen && mtbuf.offen) {
return ir.CompositeConstruct(ir.GetVectorReg(addr_reg), ir.GetVectorReg(addr_reg + 1));
return ir.CompositeConstruct(ir.GetVectorReg(addr_reg), ir.GetVectorReg(addr_reg + 1));
}
if (mtbuf.idxen || mtbuf.offen) {
return ir.GetVectorReg(addr_reg);
return ir.GetVectorReg(addr_reg);
}
return IR::Value{};
}();
@ -439,7 +439,7 @@ void Translator::BUFFER_ATOMIC(AtomicOp op, const GcnInst& inst) {
const IR::Value handle =
ir.CompositeConstruct(ir.GetScalarReg(sharp), ir.GetScalarReg(sharp + 1),
ir.GetScalarReg(sharp + 2), ir.GetScalarReg(sharp + 3));
ir.GetScalarReg(sharp + 2), ir.GetScalarReg(sharp + 3));
const IR::Value value = ir.GetVectorReg(src_reg);
const IR::Value result = [&] {

5
src/shader_recompiler/ir/ir_emitter.h
View file

@ -115,12 +115,11 @@ public:
[[nodiscard]] Value BufferAtomicAnd(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicOr(const Value& handle, const Value& address,
const Value& value,
BufferInstInfo info);
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicXor(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicExchange(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
const Value& value, BufferInstInfo info);
[[nodiscard]] U32 LaneId();
[[nodiscard]] U32 WarpId();