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https://github.com/shadps4-emu/shadPS4.git
synced 2025-04-21 03:54:45 +00:00
image_view: Attempt to apply storage swizzle on format
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parent
b5836c8c20
commit
e41281cb4a
9 changed files with 28 additions and 32 deletions
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@ -207,6 +207,7 @@ public:
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message_queue.EmplaceWait(entry);
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} else {
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ForEachBackend([&entry](auto& backend) { backend.Write(entry); });
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std::fflush(stdout);
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}
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}
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@ -957,7 +957,7 @@ int PS4_SYSV_ABI sceGnmGetGpuBlockStatus() {
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}
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int PS4_SYSV_ABI sceGnmGetGpuCoreClockFrequency() {
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LOG_ERROR(Lib_GnmDriver, "(STUBBED) called");
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LOG_DEBUG(Lib_GnmDriver, "(STUBBED) called");
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return ORBIS_OK;
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}
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@ -149,6 +149,9 @@ Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp) {
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// Attribute is disabled or varying component is not written
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return ctx.ConstF32(comp == 3 ? 1.0f : 0.0f);
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}
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if (param.is_default) {
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return ctx.OpCompositeExtract(param.component_type, param.id, comp);
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}
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if (param.num_components > 1) {
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const Id pointer{
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@ -208,7 +211,7 @@ Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, u32 comp) {
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void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 element) {
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const Id pointer{OutputAttrPointer(ctx, attr, element)};
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ctx.OpStore(pointer, value);
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ctx.OpStore(pointer, ctx.OpBitcast(ctx.F32[1], value));
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}
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Id EmitLoadBufferU32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address) {
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@ -205,7 +205,7 @@ void EmitContext::DefineInputs(const Info& info) {
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: 1;
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// Note that we pass index rather than Id
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input_params[input.binding] = {
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rate_idx, input_u32, U32[1], input.num_components, input.instance_data_buf,
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rate_idx, input_u32, U32[1], input.num_components, false, input.instance_data_buf,
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};
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} else {
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Id id{DefineInput(type, input.binding)};
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@ -232,8 +232,8 @@ void EmitContext::DefineInputs(const Info& info) {
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for (const auto& input : info.ps_inputs) {
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const u32 semantic = input.param_index;
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if (input.is_default) {
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input_params[semantic] = {MakeDefaultValue(*this, input.default_value), input_f32,
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F32[1]};
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input_params[semantic] = {MakeDefaultValue(*this, input.default_value), F32[1],
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F32[1], 4, true};
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continue;
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}
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const IR::Attribute param{IR::Attribute::Param0 + input.param_index};
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@ -219,6 +219,7 @@ public:
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Id pointer_type;
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Id component_type;
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u32 num_components;
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bool is_default{};
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s32 buffer_handle{-1};
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};
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std::array<SpirvAttribute, 32> input_params{};
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@ -351,7 +351,7 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
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}
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if (data_format == AmdGpu::DataFormat::Format8_8_8_8 &&
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num_format == AmdGpu::NumberFormat::Unorm) {
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return vk::Format::eB8G8R8A8Unorm;
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return vk::Format::eR8G8B8A8Unorm;
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}
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if (data_format == AmdGpu::DataFormat::Format8_8_8_8 &&
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num_format == AmdGpu::NumberFormat::Srgb) {
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@ -50,15 +50,6 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
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UNREACHABLE();
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}
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scheduler.EndRendering();
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const vk::MemoryBarrier barrier = {
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.srcAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
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.dstAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
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};
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cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eAllCommands,
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vk::PipelineStageFlagBits::eAllCommands,
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vk::DependencyFlagBits::eByRegion, barrier, {}, {});
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BeginRendering();
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UpdateDynamicState(*pipeline);
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@ -100,15 +91,6 @@ void Rasterizer::DispatchDirect() {
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UNREACHABLE();
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}
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scheduler.EndRendering();
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const vk::MemoryBarrier barrier = {
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.srcAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
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.dstAccessMask = vk::AccessFlagBits::eMemoryRead | vk::AccessFlagBits::eMemoryWrite,
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};
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cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eAllCommands,
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vk::PipelineStageFlagBits::eAllCommands,
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vk::DependencyFlagBits::eByRegion, barrier, {}, {});
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cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, pipeline->Handle());
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cmdbuf.dispatch(cs_program.dim_x, cs_program.dim_y, cs_program.dim_z);
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}
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@ -48,12 +48,19 @@ vk::ComponentSwizzle ConvertComponentSwizzle(u32 dst_sel) {
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}
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bool IsIdentityMapping(u32 dst_sel, u32 num_components) {
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return (num_components == 1 && dst_sel == 0b100) ||
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(num_components == 2 && dst_sel == 0b101100) ||
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(num_components == 3 && dst_sel == 0b110101100) ||
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return (num_components == 1 && (dst_sel == 0b100 || dst_sel == 0b001000000100)) ||
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(num_components == 2 && (dst_sel == 0b101100 || dst_sel == 0b001000101100)) ||
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(num_components == 3 && (dst_sel == 0b110101100 || dst_sel == 0b001110101100)) ||
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(num_components == 4 && dst_sel == 0b111110101100);
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}
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vk::Format TrySwizzleFormat(vk::Format format, u32 dst_sel) {
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if (format == vk::Format::eR8G8B8A8Unorm && dst_sel == 0b111100101110) {
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return vk::Format::eB8G8R8A8Unorm;
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}
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return format;
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}
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ImageViewInfo::ImageViewInfo(const AmdGpu::Image& image, bool is_storage) noexcept
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: is_storage{is_storage} {
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type = ConvertImageViewType(image.GetType());
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@ -68,13 +75,15 @@ ImageViewInfo::ImageViewInfo(const AmdGpu::Image& image, bool is_storage) noexce
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mapping.a = ConvertComponentSwizzle(image.dst_sel_w);
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// Check for unfortunate case of storage images being swizzled
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const u32 num_comps = AmdGpu::NumComponents(image.GetDataFmt());
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if (is_storage && !IsIdentityMapping(image.DstSelect(), num_comps)) {
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if (num_comps == 4) {
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printf("bad\n");
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const u32 dst_sel = image.DstSelect();
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if (is_storage && !IsIdentityMapping(dst_sel, num_comps)) {
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mapping = vk::ComponentMapping{};
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if (auto new_format = TrySwizzleFormat(format, dst_sel); new_format != format) {
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format = new_format;
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return;
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}
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LOG_ERROR(Render_Vulkan, "Storage image (num_comps = {}) requires swizzling {}", num_comps,
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image.DstSelectName());
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mapping = vk::ComponentMapping{};
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}
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}
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@ -207,7 +207,7 @@ ImageView& TextureCache::FindTexture(const ImageInfo& info, const ImageViewInfo&
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view_info_tmp.range.extent.levels > image.info.resources.levels ||
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view_info_tmp.range.extent.layers > image.info.resources.layers) {
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LOG_ERROR(Render_Vulkan,
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LOG_DEBUG(Render_Vulkan,
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"Subresource range ({}~{},{}~{}) exceeds base image extents ({},{})",
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view_info_tmp.range.base.level, view_info_tmp.range.extent.levels,
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view_info_tmp.range.base.layer, view_info_tmp.range.extent.layers,
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