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consider 3d depth alignment in size calculations
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4a589cc141
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2 changed files with 4 additions and 10 deletions
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@ -359,16 +359,16 @@ void ImageInfo::UpdateSize() {
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mip_d = std::bit_ceil(mip_d);
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mip_d = std::bit_ceil(mip_d);
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}
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}
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auto size_mode_adj =
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switch (tiling_mode) {
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tiling_idx == 0x13 ? AmdGpu::TilingMode::Texture_MicroTiled : tiling_mode;
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switch (size_mode_adj) {
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case AmdGpu::TilingMode::Display_Linear: {
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case AmdGpu::TilingMode::Display_Linear: {
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std::tie(mip_info.pitch, mip_info.size) =
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std::tie(mip_info.pitch, mip_info.size) =
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ImageSizeLinearAligned(mip_w, mip_h, bpp, num_samples);
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ImageSizeLinearAligned(mip_w, mip_h, bpp, num_samples);
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mip_info.height = mip_h;
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mip_info.height = mip_h;
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break;
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break;
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}
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}
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case AmdGpu::TilingMode::Texture_Volume:
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mip_d += (-mip_d) & 3u;
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[[fallthrough]];
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case AmdGpu::TilingMode::Texture_MicroTiled: {
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case AmdGpu::TilingMode::Texture_MicroTiled: {
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std::tie(mip_info.pitch, mip_info.size) =
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std::tie(mip_info.pitch, mip_info.size) =
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ImageSizeMicroTiled(mip_w, mip_h, bpp, num_samples);
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ImageSizeMicroTiled(mip_w, mip_h, bpp, num_samples);
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@ -11,12 +11,6 @@ namespace VideoCore {
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class TextureCache;
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class TextureCache;
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/// Converts tiled texture data to linear format.
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void ConvertTileToLinear(u8* dst, const u8* src, u32 width, u32 height, bool neo);
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/// Converts image format to the one used internally by detiler.
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vk::Format DemoteImageFormatForDetiling(vk::Format format);
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enum DetilerType : u32 {
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enum DetilerType : u32 {
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Micro8x1,
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Micro8x1,
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Micro8x2,
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Micro8x2,
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